CS2300P-CZZR Cirrus Logic Inc, CS2300P-CZZR Datasheet - Page 12

• Manufacturer Part Number: CS2300P-CZZR
• Description: IC General Purpose PLL LCO
• Manufacturer: Cirrus Logic Inc
• Type: Fanout Distribution, Fractional N Synthesizerr

Specifications of CS2300P-CZZR

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 75MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Frequency-max: 75MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1494 - BOARD EVAL GEN PURPOSE PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12
5.3.2
SDATA
remain continuous throughout the missing CLK_IN period including the time while the PLL re-acquires
lock.
Adjusting the Minimum Loop Bandwidth for CLK_IN
The CS2300 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and
128 Hz using the ClkIn_BW[2:0] global parameter. The minimum loop bandwidth of the Digital PLL direct-
ly affects the jitter transfer function; specifically, jitter frequencies below the loop bandwidth corner are
passed from the PLL input directly to the PLL output without attenuation. In some applications it is desir-
able to have a very low minimum loop bandwidth to reject very low jitter frequencies, commonly referred
to as wander. In others it may be preferable to remove only higher frequency jitter, allowing the input wan-
der to pass through the PLL without attenuation.
Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys-
tem clocks and associated data are derived will benefit from the maximum jitter and wander rejection of
the lowest PLL bandwidth setting. See
Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data
are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the
system. See
necessary to increase the minimum loop bandwidth allowing this wander to pass through to the CLK_OUT
ClkSkipEn=1
ClkOutUnl=0 or 1
Referenced Control
ClkSkipEn..............................“Clock Skip Enable (ClkSkipEn)” on page 21
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 22
MCLK
LRCK
SCLK
Wander > 1 Hz
PLL_OUT
UNLOCK
Figure
CLK_IN
D0
9. If there is substantial wander on the CLK_IN signal in these applications, it may be
Figure 8. Low bandwidth and new clock domain
Jitter
Parameter Definition
ClkSkipEn=0
ClkOutUnl=0
D1
CLK_IN
Figure 7. CLK_IN removed for < t
or
Confidential Draft
PLL_OUT
UNLOCK
CLK_IN
Figure
BW = 1 Hz
t
CS
PLL
3/18/09
8.
from new clock domain.
Subclocks generated
PLL_OUT
ClkSkipEn=0
ClkOutUnl=1
Lock Time
PLL_OUT
UNLOCK
t
CS
CLK_IN
CS
SDATA
Wander and Jitter > 1 Hz Rejected
MCLK
LRCK
SCLK
= invalid clocks
CS2300-OTP
Lock Time
D0
DS844PP2
t
CS
D1