CS4202-JQZR Cirrus Logic Inc, CS4202-JQZR Datasheet - Page 27

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CS4202-JQZR

Manufacturer Part Number
CS4202-JQZR
Description
IC AC97 W/Headphone Amplifier
Manufacturer
Cirrus Logic Inc
Type
Audio Codec '97r
Datasheet

Specifications of CS4202-JQZR

Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
1 / 1
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
90 / 90
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-TQFP, 48-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4202-JQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
4.9
Mute
GL[3:0]
GR[3:0]
Default
DS549PP2
Mute
D15
Record Gain Register (Index 1Ch)
D14
0
D13
0
source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB
gain adjustment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain. See Table 7 for
further details.
source, applied after the input mux and before the ADCs. Each step corresponds to 1.5 dB
gain adjustment, with 0000 = 0 dB. The total range is 0 dB to +22.5 dB gain. See Table 7 for
further details.
Record Gain Mute. Setting this bit mutes the input to the L/R ADCs.
Left ADC Gain. The GL[3:0] bits control the input gain on the left channel of the analog
Right ADC Gain. The GR[3:0] bits control the input gain on the right channel of the analog
8000h. This value corresponds to 0 dB gain and Mute ‘set’.
D12
0
GL3
D11
GL2
D10
Table 7. Record Gain Values
GL1
D9
Gx3 - Gx0 Gain Level
0001
0000
1111
GL0
D8
+22.5 dB
D7
+1.5 dB
0
0 dB
D6
0
D5
0
D4
0
GR3
D3
GR2
D2
CS4202
GR1
D1
GR0
D0
27

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