CS4350-CZZR Cirrus Logic Inc, CS4350-CZZR Datasheet
CS4350-CZZR
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CS4350-CZZR Summary of contents
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... Interpolation Filter with Multibit Volume Modulator Control Phase Locked Loop Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) CS4350 ® Technology for Control of Clicks Hardware Popguard Disable for Fast Startups ® Modes 127.5 dB Attenuation 1/2 dB Step Size Zero Crossing Click-Free Transitions Amp Δ ...
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... The CS4350 supports all standard digital audio interface formats, including TDM. The CS4350 is available in a 24-pin TSSOP package in both Commercial (-40° to +85°C) and Automotive grades (-40° to +105°C). The CDB4350 Customer Demonstration board is also available for device evaluation and imple- mentation suggestions ...
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... Memory Address Pointer (MAP) ................................................................................................... 27 6.4.1 INCR (Auto Map Increment Enable) .................................................................................... 27 6.4.2 MAP (Memory Address Pointer) .......................................................................................... 27 7. REGISTER QUICK REFERENCE ......................................................................................................... 28 8. REGISTER DESCRIPTION ................................................................................................................... 29 8.1 Device and Revision ID - Register 01h.......................................................................................... 29 8.2 Mode Control - Register 02h ......................................................................................................... 29 8.2.1 Digital Interface Format (DIF[2:0]) Bits 6-4 .......................................................................... 29 DS691F1 CS4350 3 ...
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... Freeze Controls (FREEZE) Bit 5.......................................................................................... 35 8.7.3 Popguard Enable (POPG_EN) Bit 4 .................................................................................... 35 8.7.4 RMCK control (RMCK_CTRL[1:0]) Bits 3:2 ......................................................................... 35 8.7.5 RMCK Ratio Select (R_SELECT[1:0]) Bits 2:1 .................................................................... 35 9. FILTER PLOTS .................................................................................................................................. 36 10. PARAMETER DEFINITIONS............................................................................................................... 38 11. PACKAGE DIMENSIONS ................................................................................................................... 39 THERMAL CHARACTERISTICS ............................................................................................................... 39 12. ORDERING INFORMATION ............................................................................................................... 40 13. REVISION HISTORY .......................................................................................................................... 40 4 CS4350 DS691F1 ...
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... Figure 27. Double-Speed (fast) Passband Detail....................................................................................... 36 Figure 28. Double-Speed (slow) Passband Detail ..................................................................................... 36 Figure 29. Quad-Speed (fast) Passband Detail ......................................................................................... 37 Figure 30. Quad-Speed (slow) Passband Detail........................................................................................ 37 LIST OF TABLES Table 1. CS4350 Auto-Detect .................................................................................................................... 18 Table 2. Digital Interface Format - Stand-Alone Mode............................................................................... 24 Table 3. Digital Interface Formats .............................................................................................................. 29 Table 4. ATAPI Decode ............................................................................................................................. 31 Table 5. Example Digital Volume Settings ................................................................................................. 33 ...
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... Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC 17 VA Analog Power (Input) - Positive power supply for the analog section 18 VQ Quiescent Voltage (Output) - Filter connection for internal quiescent voltage CS4350 RST AOUTB- AOUTB+ BMUTEC VQ GND VA VBIAS+ AMUTEC AOUTA+ AOUTA- TSTO “DAC Ana- DS691F1 ...
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... DIF0 Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial DIF1 Clock, and Serial Audio Data DIF2 De-emphasis (Input) - Selects the standard 15 μs/50 μs digital de-emphasis filter response for DEM 2 44.1 kHz sample rates DS691F1 CS4350 7 ...
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... Automotive (-DZZ ground.(Note 1) Symbol Analog power VA VLS Serial Audio Interface power VLC Control Interface power (Note Serial Audio Interface V IN-LS V IN- stg CS4350 Min Typ Max Units 4.75 5.0 5.25 V 3.14 3.3 3.46 V 1.35 3.3 5.25 V 3.14 3.3 5.25 V -40 - +85 ° ...
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... Max AC-Load Resistance Max Load Capacitance Output Impedance Notes: 3. One-half LSB of triangular PDF dither is added to data 4. R and C represent the minimum resistance and maximum capacitance required for the CS4350’s in ternal op-amp to remain stable. See DS691F1 = 25° C; Input test signal is a 997 Hz sine ...
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... Max DC Current draw from an AOUT pin Max Current draw from VQ Max AC-Load Resistance Max Load Capacitance Output Impedance Note: 5. One-half LSB of triangular PDF dither is added to data. Also, see more details on the CS4350-DZZ THD+N performance with 0dB input signal. 10 Figure 10) and output circuits as shown in Symbol Min ...
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... GND Figure 1. Equivalent Output Load Figures 3 through 5 show typical THD+N performance for CS4350 devices that exhibit the maximum full scale out- put voltages as specified in the DAC Analog Characteristics tables (see THD+N performance is increasingly affected by the full scale output voltage and temperature, with higher full scale output voltage and lower temperatures corresponding to lower THD+N performance ...
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... Fs = 44.1 kHz kHz Slow Roll-Off (Note 9) -0.01 dB corner (Single Speed) -0.1 dB corner (Double Speed) -0.2 dB corner (Quad Speed corner (All Speed Modes) Single Speed -0.01 Double Speed, Quad Speed -0.02 .583 kHz Fs = 44.1 kHz kHz CS4350 Typ Max 0 - .454 .499 - +0. ...
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... VA 5.25 V and 3.14 V VLS t sckh t sckl t lcks t lckd t lrckh t fsh t fss ≤ ≤ VA < 4. 1.35 V VLS < 3. sckh t sckl t lcks t lckd t lrckh t fsh t fss CS4350 Min Max Units 5.25 V 7.680 55.3 MHz 108 kHz 120 216 5. 55.3 MHz ...
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... L Symbol f scl t irs t buf t hdst t low t high t sust t hdd t sud susp t ack t high t t sud t ack hdd Figure 8. Control Port Timing - I²C Format CS4350 t lrckh t t fsh sckh MSB Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 300 fc 4 ...
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... CDOUT DS691F1 = 20 pF. L Symbol f sclk t srs t spi t csh t css t scl t sch t dsu (Note 15) t scdov t cscdo t css t scl t sch dsu scdov t scdov Figure 9. Control Port Timing - SPI Mode CS4350 Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 ns - 100 ns - 100 all other times ...
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... VLS = VLC =3.3 V (Note 17 VLS = VLC = 5.0 V (Note 18 VLS = VLC = 3.3 V (Note 18 (Note 19) VA, VLS VLC (Note 16 VLC= VLS = 5 VLC= VLS = 3.3 V (Note 19 VLC= VLS = 5 VLC= VLS = 3 kHz) PSRR (60 Hz) PSRR 10. CS4350 Min Typ Max 0.7• 2 1 0.75• 0.35• 0 ...
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... VLS AMUTEC 16 AOUTA+ 15 CS4350 AOUTA VLC BMUTEC 21 24 RST 22 AOUTB+ 4 DIF1(SCL/CCLK) AOUTB DIF0(SDA/CDIN) 2 DEM(AD0/CS) DIF2(AD1/CDOUT N.C. Figure 10. Typical Connection Diagram CS4350 +3 µF 10 µF + 0.1 µ µF Differential or Single- AOUTA ended Output Filter Differential or Single- AOUTB ended Output Filter 3.3 µ ...
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... In Control Port Mode, the Auto-Detect feature can be disabled by the Functional Mode (FM[1:0]) bits in the control port register 02h. In this state, the CS4350 will not auto-detect the correct mode based on the input sample rate (Fs). The operational mode must then be set manually according to one of the ranges ...
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... MSB -1 Figure 11. Left-Justified up to 24-Bit Data Left Channel + LSB MSB Figure 12. I² 24-Bit Data + LSB Figure 13. Right-Justified Data Table 2 on page 24 Section 5.1). For illustrations of the required Right Channel + LSB - Right Channel LSB - Right Channel - MSB CS4350 for +2 +1 LSB 19 ...
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... Time-Division Multiplex (TDM) Mode Four TDM interface modes are available that allow the CS4350 to input stereo PCM data in one of 4 time “slots”. Figure 14 shows the serial port connections necessary to input 8-channel TDM data into four CS4350 devices, and the corresponding DIF[2:0] pin or register-bit settings required for each CS4350. ...
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... Popguard is disabled. If the Popguard is enabled, see power-up timing. DS691F1 Figure 16 shows the de-emphasis curve for Fs equal to Gain dB T1=50 µs 0dB F1 F2 3.183 kHz 10.61 kHz Figure 16. De-Emphasis Curve Section 4.7 CS4350 µs Frequency Section 4.2. In this state, the control for a complete description of 21 ...
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... Popguard Transient Control The CS4350 uses a novel technique to minimize the effects of output transients during power-up and power- down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters activated inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors ...
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... The Cirrus Application Note titled Design Notes for a 2-Pole Filter with Differential Input, available as AN48 at www.cirrus.com, discusses the second-order Butterworth filter and differential-to-single-ended converter that was implemented on the CS4350 evaluation board, CDB4350. implementation. If only single-ended outputs from the CS4350 are required, the passive output filter shown in Figure 18 can be used ...
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... RMCK and VLS. 24 and Figure 15. DESCRIPTION 0 Left-Justified 24-bit data I² 24-bit data 1 0 Right-Justified, 16-bit data Right-Justified, 24-bit data 1 0 TDM slot 0 TDM slot TDM slot 2 TDM slot 3 1 CS4350 Figures 11-13. For all formats, SDIN is valid FORMAT FIGURE DS691F1 ...
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... MAP. The MAP register will contain the address of the last register written to the DS691F1 ”Register Description” on page Figure 19 for the clock to data relationship). There pin. AD1 and AD0 6.1) is set to 1, repeat the previous step until all the desired registers are CS4350 29). The oper- 14. 14. 25 ...
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... I²C read is the first operation performed on the MAP BYTE DATA INC 7 6 ACK ACK Figure 19. Control Port Timing, I²C Mode 6.1) is set to 1, repeat the previous step until all the desired registers are CS4350 DATA +1 DATA + ACK ACK 15. DS691F1 STOP ...
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... MAP (Memory Address Pointer) Default = ‘0000’ DS691F1 15. Section 6.1) is set to 1, keep CS low and continue providing clocks on CCLK DATA LSB MSB 1001111 Figure 20. Control Port Timing, SPI Mode Reserved MAP3 CS4350 ”Switching R/W LSB MSB MSB LSB MAP2 MAP1 MAP0 ...
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... DIF0 INVERTA INVERTB Reserved Reserved MUTEC MUTE_A A VOL6 VOL5 VOL4 VOL6 VOL5 VOL4 SZC0 RMP_UP RMP_DN Reserved FREEZE POPG_EN CS4350 RevID2 RevID1 - - - DEM1 DEM0 FM1 ATAPI3 ATAPI2 ATAPI1 MUTE_B Reserved Reserved Reserved VOL3 VOL2 VOL1 VOL3 VOL2 VOL1 Reserved FILT_SEL Reserved ...
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... DIF0 DEM1 Figures 11-13. Description Left-Justified 24-bit data 0 1 I² 24-bit data Right-Justified, 16-bit data 0 1 Right-Justified, 24-bit data TDM slot TDM slot 1 TDM slot TDM slot 3 Table 3. Digital Interface Formats CS4350 Rev2 Rev1 Rev0 - - - DEM0 FM1 FM0 Format Figure (Default ...
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... When set to 1, this bit inverts the signal polarity of channel A. When set to 0 (default), this function is disabled. This function is only available for Left Justified, Right Justified 16, and Right Justified 24 data formats. 30 Figure 21 Reserved ATAPI3 CS4350 Gain dB T1=50 µs 0dB µs -10dB F1 F2 Frequency 3.183 kHz 10.61 kHz Figure 21. De-Emphasis Curve 2 ...
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... This function is only available for Left Justified, Right Justified 16, and Right Justified 24 data formats. 8.3.4 ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0 Default = 1001 - AOUTA=aL, AOUTB=bR (Stereo) Function: The CS4350 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 4 and Figure 22 for additional information. ...
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... Volume and Mixing Control register. The corresponding MUTEC pin will go active following any ramping due to the soft and zero cross function. When set to 0 (default), this function is disabled. 32 AOUTA a[(L+R)/ a[(L+R)/ a[(L+R)/ a[(L+R)/2] Table 4. ATAPI Decode MUTE_A MUTE_B CS4350 AOUTB MUTE bR bL b[(L+R)/2] MUTE bR bL b[(L+R)/ Reserved Reserved Reserved DS691F1 ...
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... Table 5. Example Digital Volume Settings RMP_DN Reserved Description 0 Immediate Change 1 Zero Cross 0 Soft Ramp 1 Soft Ramp on Zero Crossings CS4350 VOL2 VOL1 VOL0 Table 5. The volume changes are imple- Volume Setting 0 dB -0.5 dB -3.0 dB -127 FILT_SEL Reserved Reserved 0 ...
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... Function: When set to 1 the entire device will enter a low-power state and the contents of the control registers will be retained. The power-down bit defaults to ‘0’ on power-up. 34 ”Combined Interpolation & On-Chip Analog Filter Re- Figures POPG_EN RMCK_CTRL1 RMCK_CTRL0 R_SELECT1 CS4350 through 30 R_SELECT0 DS691F1 ...
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... LRCK for 48 kHz and 96 kHz, 128x @ 192kHz 1 512x @ 48kHz, 256x @ 96 kHz, 128x @ 192kHz 0 Manual control (see RMCK Ratio Select) 1 RMCK pin driven low R_SELECT0 RMCK/LRCK Ratio ”Switching Specifications - Serial Audio Interface” on page CS4350 Section 4.7 on page 512 256 128 64 13. 22. 35 ...
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... Figure 28. Double-Speed (slow) Passband Detail CS4350 0.5 0.6 0.7 0.8 0.9 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.1 0.15 0.2 ...
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... Frequency (normalized to Fs) Figure 29. Quad-Speed (fast) Passband Detail DS691F1 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0.2 0.25 0.3 0 Figure 30. Quad-Speed (slow) Passband Detail CS4350 0.05 0.1 0.15 0.2 0.25 Frequency (normalized to Fs) 0.3 37 ...
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... The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. Intra-Channel Phase Deviation The deviation from linear phase within a given channel. Inter-Channel Phase Deviation The difference in phase between channels. 38 CS4350 DS691F1 ...
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... JEDEC #: MO-153 Controlling Dimension is Millimeters. Symbol Single-Layer PCB θ JA Multi-Layer PCB CS4350 1 E1 END VIEW L MILLIMETERS NOTE NOM MAX -- 1.10 -- 0.15 0.90 0.95 0.245 0.30 2,3 7.80 7.90 6.40 6.50 4 ...
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... CL represent the minimum resistance and maximum 9. “I²C Mode” on page 25 and 4, and Figure 5 on page 11. 16. CS4350 Container Order# Rail CS4350-CZZ Tape and Reel CS4350-CZZR Rail CS4350-DZZ Tape and Reel CS4350-DZZR - - CDB4350 and “Typical Connection Diagram” “SPI Mode” on page 26. Section 6.2 on page 25. ...
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... Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² registered trademark of Philips Semiconductor SPI is a trademark of Motorola, Inc. DS691F1 www.cirrus.com. CS4350 41 ...