CS5343-DZZ Cirrus Logic Inc, CS5343-DZZ Datasheet - Page 16
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CS5343-DZZ
Manufacturer Part Number
CS5343-DZZ
Description
IC,A/D CONVERTER,DUAL,24-BIT,TSSOP,10PIN
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS5343-CZZ.pdf
(22 pages)
Specifications of CS5343-DZZ
Number Of Bits
24
Sampling Rate (per Second)
108k
Data Interface
Serial
Number Of Converters
2
Power Dissipation (max)
85mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
10-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1156 - BOARD EVAL FOR CS5343 STEREO ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1689
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CS5343-DZZR
Manufacturer:
CIRRUS
Quantity:
6 000
16
4.4.1
4.5
Grounding and Power Supply Decoupling
As with any high-resolution converter, designing with the CS5343/4 requires careful attention to power sup-
ply and grounding arrangements if its potential performance is to be realized.
mended power arrangements, with VA connected to a clean supply. Decoupling capacitors should be as
near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially
clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the mod-
ulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize
the electrical path from FILT+ to GND. The CDB5343 evaluation board demonstrates the optimum layout
and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS
inputs.
Component Values
Three parameters determine the values of resistors R1 and R2 as shown in
attenuation, and input impedance.
Figure 7
the discussion above, this circuit provides an optimal interface for both the ADC and the signal source.
First, consumer equipment frequently requires an input impedance of 10 kΩ, which the 4.99 kΩ resistors
provide. Second, this circuit will attenuate a typical line level voltage, 2 Vrms, to the full-scale input of the
ADC, 1 Vrms when VA = 5 V. Finally, at 2.5 kΩ, the source impedance optimizes analog performance of
the ADC.
•
•
•
Source Impedance: Source impedance is defined as the impedance as seen from the ADC looking
back into the signal network. The ADC achieves optimal THD+N performance with a source imped-
ance less than or equal to 2.5 kΩ.
Attenuation: The required attenuation factor depends on the magnitude of the input signal. The full-
scale input voltage is specified under
The user should select values for R1 and R2 such that the magnitude of the incoming signal multiplied
by the attenuation factor is less than or equal to the full-scale input voltage of the device.
Input Impedance: Input impedance is the impedance from the signal source to the ADC analog input
pins, including the ADC. Because the ADC’s input impedance (see the
mercial Grade
typically used for the input attenuator, its contribution can be neglected when calculating the input im-
pedance.
tenuator.
illustrates an example configuration using two 4.99 kΩ resistors in place of R1 and R2. Based on
Table 6
(-CZZ)” table on
Input
Figure 7. CS5343/4 Example Analog Input Network
shows the input parameters and the associated design equations for the input at-
Source Impedance
Attenuation Factor
Table 6. Analog Input Design Parameters
4.99 kΩ
4.99 kΩ
Input Impedance
Table 6
page
“Analog Characteristics - Commercial Grade (-CZZ)” on page
6) is several orders of magnitude larger than the resistor values
1 µF
180pF
C0G
shows the design equation used to determine these values.
4/2/08
Draft
(
------------------------ -
------------------------ -
(
(
R1 R2
R1
R1
R1
(
R2
×
+
+
+
CS5343/4
AIN
R2
R2
R2
)
)
)
)
“Analog Characteristics - Com-
Figure
Figure 3
6: source impedance,
shows the recom-
CS5343/4
DS687F3
6.