CS5368-DQZR Cirrus Logic Inc, CS5368-DQZR Datasheet - Page 15

• Manufacturer Part Number: CS5368-DQZR
• Description: IC,A/D CONVERTER,OCTAL,24-BIT,QFP,48PIN
• Manufacturer: Cirrus Logic Inc

18
SERIAL AUDIO INTERFACE - I²S/LJ TIMING
The serial audio port is a three-pin interface consisting of SCLK, LRCK and SDOUT.
Logic "0" = GND = 0 V; Logic "1" = VLS; C
Notes:
Sample Rates
SCLK Frequency
SCLK Period
SCLK Duty Cycle
LRCK setup
LRCK hold
SDOUT setup
SDOUT hold
1. In Master mode, the SCLK/LRCK ratio is fixed at 64. In Slave Mode, the SCLK/RCLK ratio can be set ac-
cording to preference. However, chip performance is guaranteed only when using the ratios in
4.6.9 Master and Slave Clock Frequencies on page
SDOUT
SCLK
LRCK
1
Parameter
data
channel
t
Double-Speed Mode
HOLD1
Single-Speed Mode
Quad-Speed Mode
before SCLK rising
before SCLK rising
after SCLK rising
after SCLK rising
1/(64*216 kHz)
L
= 30 pF, timing threshold is 50% of VLS.
Figure 2. I²S/LJ Timing
t
PERIOD
Symbol
t
t
t
t
t
PERIOD
SETUP1
SETUP2
HOLD1
HOLD2
t
HIGH
t
SETUP2
-
-
-
-
29.
channel
t
SET UP1
72.3
Min
data
108
54
30
20
20
10
10
2
-
t
HOLD2
t
64*Fs
HIGH
Typ
-
-
-
-
-
-
-
-
-
Max
108
216
54
70
-
-
-
-
-
-
CS5368
DS624A1
Section
Unit
kHz
kHz
kHz
Hz
ns
ns
ns
ns
ns
%