CS5505-ASZR Cirrus Logic Inc, CS5505-ASZR Datasheet
CS5505-ASZR
Specifications of CS5505-ASZR
Related parts for CS5505-ASZR
CS5505-ASZR Summary of contents
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... P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com Description The CS5505/6/7/8 are a family of low power CMOS A/D converters which are ideal for measuring low-frequency signals representing physical, chemical, and biological processes. The CS 5507/8 have single-channel differential analog and reference inputs while the CS5505/6 have four pseudo-differential analog input channels ...
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... Notes: 1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the master clock frequency. Both sour ce resistance and shunt capacitance are therefore critical in determining the CS5505/6/7/8’s source impedance requirements. For more information refer to the text section Analog Input Impedance Consi derations. ...
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... FS ppm FS 0.0000238 0.24 0.0000477 0.47 0.0000954 0.95 0.0001907 1.91 0.0003814 3.81 VREF = 2.5V CS5506/8; 20-Bit Unit Conversion Factors Symbol out f -3dB t s CS5505/6/7/8 CS5505/6/7 Ω with a source CS5508-S Max Min Typ Max -55 to +125 - 0.0015 0.003 - ±32 - ±8 ± ± ± ...
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... I - 340 450 Total I - 300 - Analog Digital (Note 7) - 3.2 4 CS5505/6/7/8 CS5505/6/7/8 = 1kΩ with a source CS5507/8-S Min Typ Max Units -55 to +125 ° +2.5 Volts Volts ±2.5 - 105 - dB 120 - - dB - 120 - (VA+)-2.5 - Volts - - 4 ppm/°C - 1.5 - mV/Volt - 50 - µV p µ µ ...
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... OZ C out ( MIN MAX Symbol XIN V IH M/SLP VIH V IH XIN V IL M/SLP VIL V IL (Note 8) V SLP V = -400 µ 400 µ out CS5505/6/7/8 CS5505/6/7/8 ; VA+VD ± 10%; VA-= -5V ± 10%; Min Typ Max 3 0.9VD 2 1 0.1VD 0.8 0.45VD+ 0.5VD+ 0.55VD+ (VD+)-1 0 ± ...
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... CS5505/6/7/8 CS5505/6/7/8 Typ Max Units 32.768 53.0 kHz 32.768 34.0 kHz - 163 kHz - 1.0 µ 1.0 µ 500 - clk ...
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... CS5505/6/7/8 CS5505/6/7/8 Typ Max Units 32.768 53.0 kHz 32.768 34.0 kHz - 163 kHz - 1.0 µ 1.0 µ 500 - clk ...
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... CAL CONV STATE Standby XIN XIN/2 A0 CONV DRDY BP/UP STATE Standby ccw t t scl cal Calibration Figure 1. Calibration Timing (Not to Scale) t hca sac t cpw t t scn Conversion Figure 2. Conversion Timing (Not to Scale) CS5505/6/7/8 CS5505/6/7/8 Standby t bus t buh con Standby DS59F7 DS59F4 ...
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... SCLK rising to SDATA Hi-Z t fd2 f sclk Pulse Width High t ph2 Pulse Width Low t pl2 t csd2 (Note 18) t dd2 t fd3 t fd4 CS5505/6/7/8 CS5505/6/7/8 VA+, VD ± 10%; MAX pF.) (Note 2) Min Typ Max - - 2/fclk - 2/f 3/f clk clk - 80 250 - 1/f - clk - 1/f - clk ...
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... SCLK rising to SDATA Hi-Z t fd2 f sclk Pulse Width High t ph2 Pulse Width Low t t csd2 (Note 18) t dd2 t fd3 SCLK falling to SDATA Hi-Z t fd4 CS5505/6/7/8 CS5505/6/7/8 VA ± 10%; VD+ = 3.3V ± MAX = 50 pF.) (Note 2) L Min Typ Max - - 2/fclk - 2/f 3/f clk clk - 265 400 - ...
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... Figure 4. Timing Relationships; SEC Mode (Not to Scale) DS59F7 DS59F4 t csd1 Standby t ph1 pl1 dd1 cd1 MSB MSB-1 Conversion2 MSB MSB-1 MSB-2 t dd2 MSB MSB-1 LSB dd2 ph2 t pl2 CS5505/6/7/8 CS5505/6/7/8 Conversion Hi-Z t fd2 Hi-Z LSB+1 LSB t fd3 LSB+1 LSB t fd4 11 11 ...
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... REF and -VREF remain inside the supply values of VA+ and VA-. 21. The CS5505/6/7/8 can acc ept input voltages up to the analog suppl ies (VA+ and VA-). In unipolar mode the CS5505/6/7/8 wil l output all 1’s if the dc input magnitude ( (AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all 0’ ...
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... GENERAL DESCRIPTION The CS5505/6/7/8 are very low power mono- lith A/D co nverters designed specifically for measurement of dc signals. The CS5505/7 are 16-bit converters (a four channel and a single channel version). The CS5506/8 are 20-bit converters (a four channel and a single channel version). Each of the devices includes a ...
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... Note that any time CONV transitions from low to high, the multiplexer inputs A0 and A1 are latched internal to the CS5505 and CS5506 de- vices. These latched inputs select the analog input channel which will be used once conver- sion commences ...
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... BP/UP can be changed at the same time as A0 and A1. The digital filter in the CS5505/6/7/8 has a Fi- nite Impulse Response and is designed to settle to full accuracy in one conversion time. There- fore, the multiplexer can be changed at the conversion rate ...
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... The com- mon mode voltage range of the external reference can allow the reference to lie at any voltage between the VA+ and VA- supply rails. Figures 5 and 6 illustrate how the CS5505/6/7/8 converters are connected for external and for in- ternal voltage reference use, respectively. Analog Input Range ...
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... Converter Performance The CS5505/6/7/8 A/D converters have excellent linearity performance. Calibration minimizes the errors in offset and gain. The CS5505/7 devices have no missing code performance to 16-bits. The CS5506/8 devices have no missing code performance to 20-bits. Figure 7 illustrates the DNL of the 16-bit CS5505. The converters ...
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... CS5505 (1/4LSB at 16-bits) and 600 nV in the CS5506 (1/4LSB at 20-bits), the above equa- tion indicates that when operating from a 32.768 kHz XIN, source resistances up to 110 kΩ in the CS5505 or 84 kΩ in the CS5506 15 pF are acceptable in the absence of external capaci- Internal tance (C EXT = 0) ...
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... Digital Filter Characteristics The digital filter in the CS5505/6/7/8 is the com- bination of a comb filter and a low pass filter. The comb filter has zeros in its transfer function which are optimally placed to reject line interfer- ence frequencies (50 and 60 Hz and their multiples) when the CS5505/6/7/8 is clocked at 32 ...
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... If the CS5505/6/7/8 is operated at a clock rate other than 32.768 kHz, the filter characteristics, including the comb filter zeros, will scale with the operating clock frequency. Therefore, opti- mum rejection of line frequency interference will occur with the CS5505/6/7/8 running at 32.768 kHz. The CS5505/6/7/8 can be used with external clock rates from 30 kHz to 163 kHz ...
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... Synchronous Self-Clocking Mode The serial port operates in the SSC mode when the M/SLP pin is connected to the VD+ pin on the part. In SSC mode the CS5505/6/7/8 fur- nishes both the serial output data (SDATA) and the serial clock (SCLK). When the serial port is updated at the end of a conversion, DRDY falls. ...
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... Figure 13. Sleep Threshold Control of 10 µA maximum. Power Supplies and Grounding The analog and digital supply pins to the CS5505/6/7/8 are brought out on separate pins to minimize noise coupling between the analog and digital sections of the chip. Note that there is no CS5505/6/7/8 CS5505/6/7/8 ...
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... Voltage Reference - Note: To use the internal 2.5 volt reference see Figure 6. Figure 14. CS5505/6 System Connection Diagram Using External Reference, Single Supply DS59F7 DS59F7 VD+ or DGND pins; VD+ must remain more positive than the DGND pin. The following power supply options are possi- ...
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... Analog Supply Note: To use the internal 2.5 volt reference see Figure 6. Figure 15. CS5505/6 System Connection Diagram Using External Reference, Dual Supplies 24 24 Figure 16 illustrates the CS5505/6 using dual supplies of +10V analog and +5V digital. When using separate supplies for VA+ and VD+, VA+ must be established first ...
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... AIN- + Voltage (1) Reference - Note: (1) To use the internal 2.5 volt reference see Figure 6. (2) VD+ must never exceed VA+. Examine power-up conditions. Figure 16. CS5505/6 System Connection Diagram Using External Reference, DS59F7 DS59F4 0.1 µF (2) 17 VA+ VD+ 4 CAL XOUT ...
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... VREFOUT VOLTAGE REFERENCE OUTPUT VREF- AIN- VREF CS5505/6/7/8 CS5505/6/7/8 MULTIPLEXER SELECTION INPUT DATA READY SERIAL DATA O UTPUT SERIAL CLOCK INPUT/OUTPUT POSITIVE DIGITAL POWER DIGITAL GROUND NEGATIVE ANALOG POWER POSITIVE ANALOG POWER VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT ...
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... SCLK - Serial Clock Input/Output, Pin 18 (21). A clock signal on this pin determines the output rate of the data from the SDATA pin. The M/SLP pin determines whether SCLK is an input or and output. When used as an input, it must not be allowed to float. DS59F7 DS59F7 CS5505/6/7/8 CS5505/6/7 ...
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... AIN+, AIN-, (AIN1+, AIN2+, AIN3+, AIN4+, AIN-) - Differential Analog Inputs, Pins 8, 10 (9, 10, 12, 13, 11). AIN- in the CS5505 common measurement node for AIN1+, AIN2+, AIN3+ and AIN4+. VREF+, VREF- - Differential Voltage Reference Inputs, Pins 11, 12 (14, 15). A differential voltage reference on these pins operates as the voltage reference for the converter ...
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... Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (011...111 to 100...000) from the ideal ( the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs DS59F7 DS59F7 CS5505/6/7/8 CS5505/6/7/8 3 ⁄ 1 LSB above the voltage on the AIN- 2 ⁄ ...
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... ORDERING INFORMATION Model Resolution CS5505-ASZ (lead free) CS5506-BSZ (lead free) CS5507-ASZ (lead free) CS5508-BSZ (lead free) ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5505-ASZ (lead free) CS5506-BSZ (lead free) CS5507-ASZ (lead free) CS5508-BSZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. ...
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... TORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS59F7 www.cirrus.com CS5505/6/7/8 Changes 31 ...
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... NOTES - CS5505/6/7/8 DS59F7 ...
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... FAX: (512) 445 7581 http://www.crystal.com Description The CDB5505/ 5506/5507/5508 rcuit boa signed to provide quick evaluation of the CS5505/6/7/8 series of A/D converters. The board can be configured to evaluate the CS5505/6/7/8 in either SSC (Synchronous Self-Clocking) or SEC (Synchronous External-Clocking) serial port mode. ...
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... Self-Clocking) or the SEC (Synchronous Exter- nal Clocking) mode. See the device data sheet for an explanation of these modes. All of the control pins of the CS5505/6/7/8 are available at the J1 header connector. Buffer ICs U2 and U3 are used to buffer the converter for interface to off-board circuits. The buffers are ...
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... DS59DB4 DS59DB2 CDB5505/6/7/8 CS5505/6/7 ...
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... XIN 5/4 17/20 XOUT 6/5 16/19 M/SLP 7/6 15/18 BU/UP 8/7 14/17 AIN1+ 9/8 13/16 AIN2+/NC 10/9 12/15 AIN- 11/10 11/14 AIN3 Figure 2. CS5505/6 and CS5507/8 Pin Layouts CDB5505/6/7/8 CS5505/6/7/8 A1 DRDY SDATA SCLK VD+ DGND VA- VA+ VREFOUT VREF- VREF+ AIN4+ DS59DB4 DS59DB2 ...
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... Figure 3. Top Ground Plane Layer (NOT TO SCALE) DS59DB4 DS59DB2 CDB5505/6/7/8 CS5505/6/7 ...
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... Figure 4. Bottom Trace Layer (NOT TO SCALE CDB5505/6/7/8 CS5505/6/7/8 DS59DB4 DS59DB2 ...
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... DS59DB4 DS59DB2 Figure 5. Silk Screen Layer (NOT TO SCALE) CDB5505/6/7/8 CS5505/6/7 ...
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REVISION HISTORY Revision Date DB2 MAR 1995 First Release F5 AUG 2005 Updated legal notice. DB4 JUN 2009 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to ...