CS5529-ASZR Cirrus Logic Inc, CS5529-ASZR Datasheet
CS5529-ASZR
Specifications of CS5529-ASZR
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CS5529-ASZR Summary of contents
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... VREF- Latch http://www.cirrus.com General Description The 16-bit CS5529 is a low-power, programmable ∆Σ ADC (Analog-to-Digital Converter), coarse/fine charge buffers, a fourth-order ∆Σ modulator, a calibration microcontroller, a digital filter with program- mable decimation rates, a 6-bit output latch, and a three- wire serial interface. The ADC is designed to operate from single or dual analog supplies and a single digital supply ...
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... Performing Conversions with PF bit = 0 ............................................. 21 Performing Conversions with PF bit = 1 ............................................. 21 Single Conversion ........................................................................ 21 Continuous Conversions .............................................................. 21 Output Coding .................................................................................... 22 ............................................................................................................ 22 Power Supply Arrangements .................................................................... 23 Getting Started ......................................................................................... 25 PCB Layout .............................................................................................. 25 PIN DESCRIPTIONS ......................................................................................... 26 SPECIFICATION DEFINITIONS ........................................................................ 28 ORDERING INFORMATION .............................................................................. 29 ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ...... 29 PACKAGE DIMENSIONS ................................................................................. 30 2 Offset Register ...................................................................... 17 Gain Register ........................................................................ 18 CS5529 DS246F5 ...
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... Command and Data Word Timing. ............................................................ 14 Filter Response (Normalized to Output Word Rate = 1)............................ 16 Self Calibration of Offset. .......................................................................... 18 Self Calibration of Gain. ............................................................................ 18 System Calibration of Offset...................................................................... 18 System Calibration of Gain........................................................................ 19 CS5529 Configured with a +5.0 V Analog Supply..................................... 23 CS5529 Configured with ±2.5 V Analog Supplies. .................................... 23 CS5529 Configured with ±3.0 V Supplies. ................................................ 24 REVISION HISTORY Revision Date F4 Sep ‘ ...
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... For peak-to-peak noise multiply by 6.6 for all ranges and output rates. Specifications are subject to change without notice °C; VA± = ±2.5 V ±5%, VD ±5%, VREF (Note 3) (Note 3) (Notes 3 and 4) (Note Filter Frequency (Hz) 1.64 3.27 6.55 12.7 25.4 50.4 70.7 84.6 CS5529 Min Typ Max - ±0.0015 ±0.003 % ±1 ±2 LSB - ±2 ±4 LSB ...
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... All outputs unloaded. All inputs CMOS levels. Power consumption scales linearly with changes in supply voltage. DS246F5 (Continued) Min (Bipolar/Unipolar Mode) 0.0 VA (Note 7) - (Note 8) 1.0 (Bipolar/Unipolar Mode) - (Note 9) 1.0 VA- VA (Note (Note 10 CS5529 Typ Max Unit - VA VA+ V 120 - dB 120 - 3 ±1. VA+ ...
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... XIN (VD+)-0 SCLK (VD+)-0. XIN, SCLK V IL XIN V IL SCLK V IL SDO -400 µA V (VD+)-0.3 out OH (VD+)-1.0 SDO -5 out OH SDO 400 µA V out OL SDO 5 out out Symbol CS5529 Min Typ Max Unit - - ±1 ±10 µ ±10 µ ...
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... Normal operation is not guaranteed at these extremes. DS246F5 (DGND = 0 V) (See Note 13.) Symbol (Notes 14 and 15) Positive Digital VD+ Positive Analog VA+ Negative Analog VA- (Notes 16 and 17 OUT (Note 18) PDN AIN and VREF pins V INA V IND stg CS5529 Min Typ Max -0.3 - +6.0 -0.3 - +6.0 -6 ± ± (VA-) + (-0.3) - (VA+)+0.3 -0.3 - (VD+)+0 ...
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... Symbol (Note19) (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output XTAL = 32.768 kHz (Note 21) SCLK Pulse Width High Pulse Width Low CS5529 Min Typ Max XIN 30 32.768 100 rise - - 1 ...
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... CS t3 SCLK Continuous Running SCLK Timing (Not to Scale DS246F5 SDI Write Timing (Not to Scale SDO Read Timing (Not to Scale) CS5529 ...
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... Hz and 60 Hz line interference simultaneously. Analog Input The CS5529 provides a nominal 2.5 V input span when the gain register is 1.0 decimal and the differ- ential reference voltage between VREF+ and VREF- is 2.5 V. The gain registers content is used during calibration to set the gain slope of the ADC’ ...
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... The differential voltage between VREF+ and VREF- sets the nominal full scale input span of the converter. For a single-ended reference voltage, such as the LT1019-2.5, the reference output is connected to the VREF+ pin of the CS5529 and the ground reference for the LT1019-2.5 is connected to the VREF- pin. Serial Port ...
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... Read from selected register. 000 Offset Register 001 Gain Register 010 Configuration Register 011 Conversion Data Register (read only) 100 Set-up Registers (Offset, Gain, Configuration) 101 Reserved 110 Reserved 111 Reserved 0 Run 1 Power Save Table 1. Command Set CS5529 D0 PS/R FUNCTION PS DS246F5 ...
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... Serial Port Interface The CS5529’s serial interface consists of four con- trol lines: CS, SDI, SDO, and SCLK. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied to logic 0, the port can function as a three wire interface. ...
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... SDO * clock cycle nve rsio n exce first co nve rsio ich w ill take clock cycle ( t giste rite C ycle ata ( for S et giste rs ) Read C ycle ontinuous C onvers ion R ead (P F bit = 1) Figure 4. Command and Data Word Timing. CS5529 LSB LSB ata DS246F5 ...
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... It only resets the serial port to the command mode. System Initialization When power to the CS5529 is applied, the chip is held in a reset condition until the 32.768 kHz oscil- lator has started and a counter-timer elapses. Due to the high Q of the 32.768 kHz crystal, the oscillator takes 400-600 ms to start ...
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... OWR doubles and the filter’s corner frequency moves to 25.4 Hz. Clock Generator The CS5529 includes a gate which can be connect- ed with an external crystal to provide the master clock for the chip. The chip is designed to operate using a low-cost 32.768 kHz “tuning fork” type crystal ...
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... Reading the configuration register alone will not clear the DF bit. 2) After the CS5529 is reset, the converter is functional and can perform measurements without being calibrated. In this case, the converter will utilize the initialized values of the on-chip registers (Gain = 1 ...
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... MSB- 22). 0 Self Calibration The CS5529 offers both self offset and self gain calibrations. For the self-calibration of offset, the converter internally ties the inputs of the modulator together and routes them to the VREF- pin as shown in Figure 6. Also self offset calibration re- quires that VREF- be tied to a fixed voltage be- tween VA+ and VA- ...
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... Factory calibration can be performed in a user’s system by using the system calibration capabilities of the CS5529. After the ADC is calibrated in the user’s system, the offset and gain register contents can be read by the system microcontroller and re- corded in EEPROM. These same calibration words ...
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... R Normal operation (no calibration) 001 Offset -- Self-Calibration 010 Gain -- Self-Calibration 011 Offset self-cal followed by Gain self-calibration 100 Not Used. 101 Offset -- System Calibration 110 Gain -- System Calibration 111 Not Used. CS5529 D16 D15 D14 D13 LPM WR2 WR1 WR0 PSS DF CC2 ...
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... Performing Conversions The CS5529 offers two modes of performing con- versions: single conversion and continuous conver- sions. The sections that follow detail the differences and provides examples illustrating how to use the modes. Note that it is assumed that the configuration register has been initialized before conversions are performed ...
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... The OD flag bit will be cleared to logic 0 when the modulator becomes sta- ble. Table 2 and Table 3 illustrate the output coding for the CS5529. Unipolar conversions are output in bi- nary format and bipolar conversions are output two's complement. D19 D18 ...
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... V Differential Inputs (Gain Register = 4.0) Common Mode = 0 to VA+ Logic Outputs: A0, A1 Switch from VA+ to VA- D0-D3 Switch from VD+ to DGND Figure 10. CS5529 Configured with a +5.0 V Analog Supply. +2.5 V Analog Supply ±2.5 V Differential Inputs (Gain Register = 1.0) ±1.25 V Differential Inputs (Gain Register = 2.0) ± ...
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... digital supply to measure ground referenced bipolar signals. Fig- ure 12 illustrates the CS5529 connected with ±3.0 +3.0 V Analog Supply ±3.0 V Differential Inputs (Gain Register = 1.0) ±1.50 V Differential Inputs (Gain Register = 2.0) ±750 mV Differential Inputs (Gain Register = 4.0) -3.0 V Analog ...
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... The converters include an on-chip power on reset circuit to automatically reset the ADCs shortly af- ter power up. When power to the CS5529 is ap- plied, the chip is held in a reset condition until the 32.768 kHz oscillator has started and a counter- timer elapses. The counter-timer counts 1002 oscil- lator clock cycles to make sure the oscillator is ful- ly stable ...
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... VOLTAGE REFERENCE INPUT VA- VREF+ VA VREF- VOLTAGE REFERENCE INPUT AIN LOGIC OUTPUT (DIGITAL LOGIC OUTPUT (DIGITAL) AIN LOGIC OUTPUT (DIGITAL SDI SERIAL DATA INPUT 7 14 SERIAL DATA OUTPUT D0 SDO VD+ POSITIVE DIGITAL POWER SCLK 9 12 DGND DIGITAL GROUND 10 11 CRYSTAL IN XOUT XIN CS5529 DS246F5 ...
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... Fully differential inputs which establish the voltage reference for the on-chip modulator. Power Supply Connections VA+ - Positive Analog Power, Pin 2. Positive analog supply voltage. VA- - Negative Analog Power, Pin 1. Negative analog supply voltage. VD+ - Positive Digital Power, Pin 13. Positive digital supply voltage (+3 V). DGND - Digital Ground, Pin 12. Digital Ground. DS246F5 CS5529 27 ...
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... AIN- pin). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs. 28 CS5529 DS246F5 ...
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... CS5529-AS ±0.003% CS5529-ASZ ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model CS5529-AP CS5529-AS CS5529-ASZ (Lead Free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS246F5 Temperature Range -40°C to +85°C 20-pin 0.3" Plastic DIP -40°C to +85°C 20-pin 0.2" Plastic SSOP -40°C to +85°C 20-pin 0.2" ...
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... CS5529 ∝ SIDE VIEW MILLIMETERS MIN MAX 0.00 5.33 0.38 0.64 2.92 4.95 0.36 0.56 1.14 1.78 0.20 ...
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... CS5529 1 E1 END VIEW L MILLIMETERS NOTE MAX -- 2.13 0.25 1.88 0.38 2,3 7.50 1 8.20 5.60 1 0.75 1.03 0° 8° ...