CS8420-CSZR Cirrus Logic Inc, CS8420-CSZR Datasheet - Page 38

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CS8420-CSZR

Manufacturer Part Number
CS8420-CSZR
Description
IC,Digital Audio Sample Rate Converter,SOP,28PIN
Manufacturer
Cirrus Logic Inc
Datasheets

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38
10.6
SIMS
SISF
SIRES[1:0]
SIJUST
SIDEL
SISPOL
SILRPOL
SIMS
7
Serial Audio Input Port Data Format (05h)
SISF
Master/Slave Mode Selector
0 - Serial audio input port is in Slave mode (default)
1 - Serial audio input port is in Master mode
ISCLK frequency (for Master mode)
0 - 64*Fsi (default)
1 - 128*Fsi
00 - 24 bit resolution (default)
01 - 20 bit resolution
10 - 16 bit resolution
11 - Reserved
Justification of SDIN data relative to ILRCK
0 - Left-Justified (default)
1 - Right-Justified
Delay of SDIN data relative to ILRCK, for left-justified data formats
0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (default)
1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge
ISCLK clock polarity
0 - SDIN sampled on rising edges of ISCLK (default)
1 - SDIN sampled on falling edges of ISCLK
ILRCK clock polarity
0 - SDIN data is for the left channel when ILRCK is high (default)
1 - SDIN data is for the right channel when ILRCK is high
Resolution of the input data, for right-justified formats
6
SIRES1
5
SIRES0
4
SIJUST
3
SIDEL
2
SISPOL
1
CS8420
SILRPOL
DS245F4
0

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