CY7C057V-15AXI Cypress Semiconductor Corp, CY7C057V-15AXI Datasheet - Page 3
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CY7C057V-15AXI
Manufacturer Part Number
CY7C057V-15AXI
Description
CY7C057V-15AXI
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C057V-15BBC.pdf
(26 pages)
Specifications of CY7C057V-15AXI
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
1.152M (32K x 36)
Speed
15ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-2105
CY7C057V-15AXI
CY7C057V-15AXI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C057V-15AXI
Manufacturer:
CYPRESS
Quantity:
201
Company:
Part Number:
CY7C057V-15AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Functional Description
The CY7C056V and CY7C057V are low-power CMOS 16K and
32K x 36 dual-port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can be
utilized as standalone 36-bit dual-port static RAMs or multiple
devices can be combined in order to function as a 72-bit or wider
master/slave dual-port static RAM. An M/S pin is provided for
implementing 72-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete
interprocessor/multiprocessor designs, communications status
buffering, and dual-port video/graphics memory.
Note
Document #: 38-06055 Rev. *E
3. CE is LOW when CE
logic.
0
V
IL
and CE
Application
1
V
IH
.
areas
include
Each port has independent control pins: Chip Enable (CE)
Read or Write Enable (R/W), and Output Enable (OE). Two flags
are provided on each port (BUSY and INT). BUSY signals that
the port is trying to access the same location currently being
accessed by the other port. The Interrupt Flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic Power-down feature is controlled independently on
each port by Chip Select (CE
The CY7C056V and CY7C057V are available in 144-Pin Thin
quad plastic flatpack (TQFP) and 172-Ball ball grid array (BGA)
packages.
0
and CE
1
) pins.
CY7C056V
CY7C057V
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