CY7C1354CV25-166BZCT Cypress Semiconductor Corp, CY7C1354CV25-166BZCT Datasheet - Page 13
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CY7C1354CV25-166BZCT
Manufacturer Part Number
CY7C1354CV25-166BZCT
Description
CY7C1354CV25-166BZCT
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1354CV25-200AXC.pdf
(30 pages)
Specifications of CY7C1354CV25-166BZCT
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
9M (256K x 36)
Speed
166MHz
Interface
Parallel
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
0°C ~ 70°C
Package / Case
165-LFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1354CV25-166BZCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK# captured in the boundary
scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
Document Number: 38-05537 Rev. *K
CS
and t
CH
). The SRAM clock input might not be
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
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