CY7C1470V33-167BZXI Cypress Semiconductor Corp, CY7C1470V33-167BZXI Datasheet - Page 9

• Manufacturer Part Number: CY7C1470V33-167BZXI
• Description: CY7C1470V33-167BZXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470V33-167BZXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Truth Table
The Truth Table for parts CY7C1470V33/CY7C1472V33/CY7C1474V33 is as follows.
Notes
Document #: 38-05289 Rev. *K
Deselect Cycle
Continue
Deselect Cycle
Read Cycle
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read
(Continue Burst)
Write Cycle
(Begin Burst)
Write Cycle
(Continue Burst)
NOP/Write Abort
(Begin Burst)
Write Abort
(Continue Burst)
Ignore Clock Edge
(Stall)
Sleep Mode
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
2. Write is defined by WE and BW
3. When a Write cycle is detected, all I/Os are tristated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power up deselected and the I/Os in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
inactive or when the device is deselected, and DQ
Operation
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
Address Used
[a:d]
. See Write Cycle Description table for details.
s
= data when OE is active.
CE
H
X
L
X
L
X
L
X
L
X
X
X
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
ADV/LD
H
H
H
H
H
L
L
L
L
X
X
L
WE
X
X
H
X
H
X
X
X
X
X
L
L
BW
H
H
X
X
X
X
X
X
X
X
L
L
x
[1, 2, 3, 4, 5, 6, 7]
OE
X
X
H
H
X
X
X
X
X
X
L
L
CEN
H
X
L
L
L
L
L
L
L
L
L
L
CLK
s
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
and DQP
X
CY7C1470V33
CY7C1472V33
CY7C1474V33
[a:d]
Data Out (Q)
Data Out (Q)
Data In (D)
Data In (D)
= tristate when OE is
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
DQ
-
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