CY7C4285V-15ASXI Cypress Semiconductor Corp, CY7C4285V-15ASXI Datasheet - Page 17

• Manufacturer Part Number: CY7C4285V-15ASXI
• Description: CY7C4285V-15ASXI
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4285V-15ASXI

• Function: Synchronous
• Memory Size: 1.1K (64 x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Configuration: Dual
• Density: 1.125Mb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 64Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 35mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Notes
Document #: 38-06012 Rev. *C
24. PAE offset − n.
25. t
26. If a read is performed on this rising edge of the read clock, there are Empty + (n−1) words in the FIFO when PAE goes LOW.
27. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255V, 16384 − (m + 1) for the CY7C4265V, 32768 − (m + 1) for the
28. PAF is offset = m.
29. 8192 − m words in CY7C4255V, 16384 − m words in CY7C4265V, 32768 − m words in CY7C4275V, and 65536 − m words in CY7C4285V.
30. 8192 − (m + 1) words in CY7C4255V, 16384 − (m + 1) words in CY7C4265V, 32768 − (m + 1) words in CY7C4275V, and 65536 − (m + 1) words in CY7C4285V.
and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK.
CY7C4275V, and 65536 − (m + 1) for the CY7C4285V.
SKEW3
WCLK
RCLK
PAF
WEN
WCLK
PAE
REN
RCLK
WEN
REN
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK
[28]
Figure 14. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
t
CLKH
(continued)
t
SKEW3
t
Figure 15. Programmable Almost Full Flag Timing
CLKH
t
ENS
[25]
t
ENH
t
CLKL
Note
Note
27
t
ENS
27
t
ENH
t
PAE synch
t
CLKL
t
PAF
t
t
ENS
ENS
FULL– M WORDS
N + 1 WORDS
IN FIFO
IN FIFO
t
ENS
CY7C4255V, CY7C4265V
CY7C4275V, CY7C4285V
[29]
t
PAF
t
ENH
FULL– (M+1) WORDS
Note
IN FIFO
26
t
PAE synch
[30]
Page 17 of 23
[+] Feedback
[+] Feedback