CY8CTST200A-48LTXIT Cypress Semiconductor Corp, CY8CTST200A-48LTXIT Datasheet - Page 205
CY8CTST200A-48LTXIT
Manufacturer Part Number
CY8CTST200A-48LTXIT
Description
CY8CTST200A-48LTXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200A-48LTXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
38
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-QFN
Processor Series
CY8CTxx2xxA
Core
M8C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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21.3.18 CMP_RDC
This register is used to read the state of the comparator data signal and the latched state of the comparator.
In the table above, reserved bits are grayed table cells and are not described in the bit description section below. Reserved
bits must always be written with a value of ‘0’. For additional information, refer to the
Comparators chapter.
Bit
5
4
1
0
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Individual Register Names and Addresses:
CMP_RDC : 0,78h
Access : POR
Bit Name
CMP1D
CMP0D
CMP1L
CMP0L
Name
Comparator Read/Clear Register
7
6
Description
Read only bit that returns the dynamically changing state of comparator 1. This bit reads zero when-
ever the comparator is disabled.
Read only bit that returns the dynamically changing state of comparator 0. This bit reads zero when-
ever the comparator is disabled.
This bit reads the latch output for comparator 1. It is cleared by either a write of ‘0’ to this bit, or by a
rising edge of the comparator 0 LUT, depending on the state of the CRST1 bit in the CMP_CR1 reg-
ister.
This bit reads the latch output for comparator 0. It is cleared by either a write of ‘0’ to this bit, or by a
rising edge of the comparator 1 LUT, depending on the state of the CRST0 bit in the CMP_CR1 reg-
ister.
CMP1D
R : 0
5
CMP0D
R : 0
4
3
Register Definitions on page 103
2
0,78h
CMP1L
RC : 0
1
CMP_RDC
CMP0L
RC : 0
0,78h
0
in the
205
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