DSPIC33FJ128GP204-E/ML Microchip Technology, DSPIC33FJ128GP204-E/ML Datasheet - Page 301
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DSPIC33FJ128GP204-E/ML
Manufacturer Part Number
DSPIC33FJ128GP204-E/ML
Description
16-bit DSC, 128KB Flash,DMA,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Specifications of DSPIC33FJ128GP204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP204-E/ML
Manufacturer:
Microchip Technology
Quantity:
135
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TABLE 27-2:
© 2011 Microchip Technology Inc.
POSCMD<1:0>
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FNOSC<2:0>
FCKSM<1:0>
RSS<1:0>
Note 1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices.
OSCIOFNC
GSS<1:0>
IOL1WAY
FWDTEN
Bit Field
WINDIS
GWRP
IESO
(1)
dsPIC CONFIGURATION BITS DESCRIPTION (CONTINUED)
FOSCSEL
FOSCSEL
Register
FSS
FWDT
FWDT
FOSC
FOSC
FOSC
FOSC
FGS
FGS
(1)
RTSP effect is
If clock switch
on any device
RTSP Effect
is enabled,
Immediate
Immediate
Immediate
Immediate
Immediate
otherwise,
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Reset;
Secure Segment RAM Code Protection
11 = No Secure RAM defined
10 = Secure RAM is 256 Bytes less BS RAM
01 = Secure RAM is 2048 Bytes less BS RAM
00 = Secure RAM is 4096 Bytes less BS RAM
General Segment Code-Protect bit
11 = User program memory is not code-protected
10 = Standard security
0x = High security
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
Two-speed Oscillator Start-up Enable bit
1 = Start-up device with FRC, then automatically switch to the
0 = Start-up device with user-selected oscillator source
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRC) oscillator with postscaler
110 = Internal Fast RC (FRC) oscillator with divide-by-16
101 = LPRC oscillator
100 = Secondary (LP) oscillator
011 = Primary (XT, HS, EC) oscillator with PLL
010 = Primary (XT, HS, EC) oscillator
001 = Internal Fast RC (FRC) oscillator with PLL
000 = FRC oscillator
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is
disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is
disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is
enabled
Peripheral pin select configuration
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
Primary Oscillator Mode Select bits
11 = Primary oscillator disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cannot be
0 = Watchdog Timer enabled/disabled by user software (LPRC
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
disabled. Clearing the SWDTEN bit in the RCON register has
no effect.)
can be disabled by clearing the SWDTEN bit in the RCON
register)
user-selected oscillator source when ready
Description
DS70292E-page 301
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