DSPIC33FJ128GP710T-I/PT Microchip Technology, DSPIC33FJ128GP710T-I/PT Datasheet - Page 157
![IC,DSP,16-BIT,CMOS,TQFP,100PIN,PLASTIC](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ128GP710T-I/PT
Manufacturer Part Number
DSPIC33FJ128GP710T-I/PT
Description
IC,DSP,16-BIT,CMOS,TQFP,100PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
3.DSPIC33FJ64GP206-IPT.pdf
(28 pages)
Specifications of DSPIC33FJ128GP710T-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164333 - MODULE SKT FOR PM3 100QFPDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP710T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ12GP201-ISO PDF datasheet
- DSPIC33FJ64GP206-IPT PDF datasheet #2
- DSPIC33FJ64GP206-IPT PDF datasheet #3
- Current page: 157 of 322
- Download datasheet (5Mb)
11.0
All of the device pins (except V
OSC1/CLKIN) are shared between the peripherals and
the parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
11.1
A parallel I/O port that shares a pin with a peripheral is,
in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1 illus-
trates how ports are shared with other peripherals and
the associated I/O pin to which they are connected.
FIGURE 11-1:
© 2009 Microchip Technology Inc.
Note:
I/O PORTS
Parallel I/O (PIO) Ports
This data sheet summarizes the features
of the dsPIC33FJXXXGPX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 10. “I/O
Ports” (DS70193) in the “dsPIC33F
Family Reference Manual”, which is avail-
able
(www.microchip.com).
from
Read TRIS
Data Bus
WR TRIS
WR LAT +
WR PORT
Read LAT
Read Port
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
the
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
Microchip
DD
TRIS Latch
Data Latch
D
D
CK
CK
, V
dsPIC33FJXXXGPX06/X08/X10
SS
Q
Q
, MCLR and
web
site
Output Multiplexers
When a peripheral is enabled and actively driving an
associated pin, the use of the pin as a general purpose
output pin is disabled. The I/O pin may be read, but the
output driver for the parallel port bit will be disabled. If
a peripheral is enabled, but the peripheral is not
actively driving a pin, that pin may be driven by a port.
All port pins have three registers directly associated
with their operation as digital I/O. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch. Reads from the port
(PORTx), read the port pins, while writes to the port
pins, write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pins will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs. An
example is the INT4 pin.
1
1
0
0
Note:
Output Enable
Output Data
The voltage on a digital input pin can be
between -0.3V to 5.6V.
Input Data
I/O
I/O Pin
DS70286C-page 155
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