DSPIC33FJ128MC802-H/SO Microchip Technology, DSPIC33FJ128MC802-H/SO Datasheet - Page 317
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DSPIC33FJ128MC802-H/SO
Manufacturer Part Number
DSPIC33FJ128MC802-H/SO
Description
16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
Specifications of DSPIC33FJ128MC802-H/SO
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REGISTER 27-3:
REGISTER 27-4:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-11
bit 10-2
bit 1-0
Note 1:
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
ADDR15
R/W-0
R/W-0
R/W-0
U-0
—
Devices with 28 pins do not have PMA<10:2>.
ADDR15: Parallel Port Destination Address bits
CS1: Chip Select 1 bit
1 = Chip select 1 is active
0 = Chip select 1 is inactive
ADDR13:ADDR0: Parallel Port Destination Address bits
Unimplemented: Read as ‘0’
PTEN14: PMCS1 Strobe Enable bit
1 = PMA14 functions as either PMA<14> bit or PMCS1
0 = PMA14 pin functions as port I/O
Unimplemented: Read as ‘0’
PTEN<10:2>: PMP Address Port Enable bits
1 = PMA<10:2> function as PMP address lines
0 = PMA<10:2> function as port I/O
PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL
0 = PMA1 and PMA0 pads functions as port I/O
PTEN14
R/W-0
R/W-0
R/W-0
R/W-0
CS1
PMADDR: PARALLEL PORT ADDRESS REGISTER
PMAEN: PARALLEL PORT ENABLE REGISTER
‘1’ = Bit is set
‘1’ = Bit is set
W = Writable bit
W = Writable bit
R/W-0
R/W-0
R/W-0
U-0
—
PTEN<7:2>
R/W-0
R/W-0
R/W-0
(1)
U-0
—
ADDR<7:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
R/W-0
R/W-0
R/W-0
U-0
—
ADDR<13:8>
R/W-0
R/W-0
R/W-0
R/W-0
PTEN<10:8>
x = Bit is unknown
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
PTEN<1:0>
DS70291E-page 317
(1)
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0
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