DSPIC33FJ12MC201-E/SO Microchip Technology, DSPIC33FJ12MC201-E/SO Datasheet - Page 204
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DSPIC33FJ12MC201-E/SO
Manufacturer Part Number
DSPIC33FJ12MC201-E/SO
Description
12 KB Flash, 1 KB RAM, 40 MIPS, 13 I/O, 16-bit Motor Control DSC, NanoWatt 20 SO
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
Specifications of DSPIC33FJ12MC201-E/SO
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC24HJ12GP201-ISO PDF datasheet
- DSPIC33FJ12MC201-ISO PDF datasheet #2
- DSPIC33FJ12MC201-ISO PDF datasheet #3
- Current page: 204 of 288
- Download datasheet (5Mb)
dsPIC33FJ12MC201/202
21.0
dsPIC33FJ12MC201/202 devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
TABLE 21-1:
DS70265D-page 202
0xF80000 FBS
0xF80002 RESERVED
0xF80004 FGS
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
Note 1:
Address
Note:
SPECIAL FEATURES
These reserved bits read as ‘1’ and must be programmed as ‘1’.
This data sheet summarizes the features
of the dsPIC33FJ12MC201/202 devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F Family Reference Manual”.
Please see the Microchip web site
(www.microchip.com) for the latest family
reference manual sections.
Name
DEVICE CONFIGURATION REGISTER MAP
FWDTEN WINDIS
PWMPIN
IESO
Bit 7
FCKSM<1:0>
—
—
Reserved
HPOL
Bit 6
(1)
—
—
—
IOL1WAY
JTAGEN
Preliminary
LPOL
Bit 5
—
—
—
—
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
WDTPRE
21.1
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
The individual Configuration bit descriptions for the
FBS, FGS, FOSCSEL, FOSC, FWDT, FPOR, and
FICD Configuration registers are shown in Table 21-2.
Note that address 0xF80000 is beyond the user program
memory space. It belongs to the configuration memory
space (0x800000-0xFFFFFF), which can only be
accessed using table reads and table writes.
The upper byte of all device Configuration registers
should always be ‘1111
appear to be NOP instructions in the remote event that
their locations are ever executed by accident. Since
Configuration bits are not implemented in the
corresponding locations, writing ‘1’s to these locations
has no effect on device operation.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
The Device Configuration register map is shown in
Table 21-1.
ALTI2C
Bit 4
Reserved
—
—
—
—
Configuration Bits
—
(1)
Bit 3
—
—
—
—
BSS<2:0>
OSCIOFNC POSCMD<1:0>
© 2009 Microchip Technology Inc.
WDTPOST<3:0>
Bit 2
1111’. This makes them
—
GSS<1:0>
FPWRT<2:0>
FNOSC<2:0>
Bit 1
ICS<1:0>
GWRP
BWRP
Bit 0
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