DSPIC33FJ16GP102T-I/SS Microchip Technology, DSPIC33FJ16GP102T-I/SS Datasheet - Page 106
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DSPIC33FJ16GP102T-I/SS
Manufacturer Part Number
DSPIC33FJ16GP102T-I/SS
Description
16-bit DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SSOP .209in T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ16GP101-IP.pdf
(322 pages)
Specifications of DSPIC33FJ16GP102T-I/SS
Core Processor
dsPIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP (0.209", 5.30mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ16GP102T-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
7.4
7.4.1
To configure an interrupt source at initialization:
1.
2.
3.
4.
7.4.2
The method used to declare an ISR and initialize the
IVT with the correct vector address depends on the
programming language (C or assembler) and the
language development tool suite used to develop the
application.
In general, the user application must clear the interrupt
flag in the appropriate IFSx register for the source of
interrupt that the ISR handles. Otherwise, program will
re-enter the ISR immediately after exiting the routine. If
the ISR is coded in assembly language, it must be
terminated using a RETFIE instruction to unstack the
saved PC value, SRL value and old CPU priority level.
DS70652C-page 106
Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
Select the user-assigned priority level for the
interrupt source by writing the control bits into
the appropriate IPCx register. The priority level
will depend on the specific application and type
of interrupt source. If multiple priority levels are
not desired, the IPCx register control bits for all
enabled interrupt sources can be programmed
to the same non-zero value.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
Enable the interrupt source by setting the inter-
rupt enable control bit associated with the
source in the appropriate IECx register.
Note:
Interrupt Setup Procedures
INITIALIZATION
INTERRUPT SERVICE ROUTINE
At a device Reset, the IPCx registers
are initialized such that all user
interrupt sources are assigned to
priority level 4.
Preliminary
7.4.3
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.4
All user interrupts can be disabled using this
procedure:
1.
2.
To enable user interrupts, the POP instruction can be
used to restore the previous SR value.
The DISI instruction provides a convenient way to
disable interrupts of priority levels 1-6 for a fixed period
of time. Level 7 interrupt sources are not disabled by
the DISI instruction.
Note:
Push the current SR value onto the software
stack using the PUSH instruction.
Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
TRAP SERVICE ROUTINE
INTERRUPT DISABLE
Only user interrupts with a priority level of
7 or lower can be disabled. Trap sources
(level 8-level 15) cannot be disabled.
© 2011 Microchip Technology Inc.
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