DSPIC33FJ16GP304-E/ML Microchip Technology, DSPIC33FJ16GP304-E/ML Datasheet - Page 31
![16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ16GP304-E/ML
Manufacturer Part Number
DSPIC33FJ16GP304-E/ML
Description
16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
2.DSPIC33FJ16GP304-IPT.pdf
(284 pages)
3.DSPIC33FJ16GP304-IPT.pdf
(8 pages)
4.DSPIC33FJ16GP304-IPT.pdf
(14 pages)
Specifications of DSPIC33FJ16GP304-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- DSPIC33FJ12MC201-ISO PDF datasheet
- DSPIC33FJ16GP304-IPT PDF datasheet #2
- DSPIC33FJ16GP304-IPT PDF datasheet #3
- DSPIC33FJ16GP304-IPT PDF datasheet #4
- Current page: 31 of 284
- Download datasheet (4Mb)
4.0
The
dsPIC33FJ16GP304 architecture features separate
program and data memory spaces and buses. This
architecture also allows the direct access of program
memory from the data space during code execution.
FIGURE 4-1:
© 2011 Microchip Technology Inc.
Note:
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
MEMORY ORGANIZATION
This data sheet summarizes the features
of
dsPIC33FJ16GP304 family of devices. It
is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
Section
(DS70202) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
dsPIC33FJ32GP202/204
the
dsPIC33FJ32GP202/204
Interrupt Vector Table
Alternate Vector Table
Device Configuration
(11264 instructions)
GOTO Instruction
Unimplemented
Reset Address
Flash Memory
User Program
dsPIC33FJ32GP202/204
PROGRAM MEMORY FOR dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
DEVICES
(Read ‘0’s)
Reserved
Registers
DEVID (2)
Reserved
Reserved
4.
“Program
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x0057FE
0x005800
0x7FFFFE
0x800000
0xF7FFFE
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFFFFFE
0xF80000
Memory”
and
and
4.1
The
dsPIC33FJ32GP202/204
devices is 4M instructions. The space is addressable by a
24-bit value derived either from the 23-bit Program Counter
(PC) during program execution, or from table operation
or data space remapping as described in
“Interfacing Program and Data Memory
User application access to the program memory space is
restricted to the lower half of the address range (0x000000
to 0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to the
Configuration bits and Device ID sections of the
configuration memory space.
The memory maps for the dsPIC33FJ32GP202/204 and
dsPIC33FJ16GP304 devices are shown in
program
Program Address Space
Alternate Vector Table
dsPIC33FJ16GP304
Interrupt Vector Table
Device Configuration
(5632 instructions)
GOTO Instruction
address
Unimplemented
Reset Address
User Program
Flash Memory
(Read ‘0’s)
Reserved
Registers
DEVID (2)
Reserved
Reserved
and
memory
dsPIC33FJ16GP304
DS70290G-page 31
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x002BFE
0x002C00
0x7FFFFE
0x800000
0xF7FFFE
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFFFFFE
0xF80000
space
Spaces”.
Figure
Section 4.6
of
4-1.
the
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