DSPIC33FJ16GP304-E/ML Microchip Technology, DSPIC33FJ16GP304-E/ML Datasheet - Page 6
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DSPIC33FJ16GP304-E/ML
Manufacturer Part Number
DSPIC33FJ16GP304-E/ML
Description
16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
2.DSPIC33FJ16GP304-IPT.pdf
(284 pages)
3.DSPIC33FJ16GP304-IPT.pdf
(8 pages)
4.DSPIC33FJ16GP304-IPT.pdf
(14 pages)
Specifications of DSPIC33FJ16GP304-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
13. Module: Product Identification
14. Module: UART
15. Module: UART
16. Module: Internal Voltage Regulator
DS80461E-page 6
Revision A2 devices marked as extended
temperature range (E) devices only support
industrial temperature range (I).
Work around
Use Revision A3 or newer devices marked as
extended temperature range (E) devices.
Affected Silicon Revisions
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
Work around
Read the error flags in the UxSTA register
whenever a byte is received to verify the error
status. In most cases, these bits will be correct,
even if the UART error interrupt fails to occur.
Affected Silicon Revisions
When the UART is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA encoder/decoder
(IREN = 1), the module incorrectly transmits a data
payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
When the VREGS bit (RCON<8>) is set to a logic
‘0’, the device may Reset and a higher sleep
current may be observed.
Work around
Ensure VREGS bit (RCON<8>) is set to a logic ‘1’
for device Sleep mode operation.
Affected Silicon Revisions
A2
A2
A2
A2
X
X
X
X
A3
A3
A3
A3
X
X
X
A4
A4
A4
A4
X
X
X
A5
A5
A5
A5
X
X
X
17. Module: PSV Operations
18. Module: I
19. Module: I
An address error trap occurs in certain addressing
modes when accessing the first four bytes of an
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (word or byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C30
version 3.11 or higher, provides the following
command-line switch that implements a work
around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C30
v3.11 tool suite for further details.
Affected Silicon Revisions
When the I
slave with and address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather
acknowledges both address bytes.
Work around
None.
Affected Silicon Revisions
With the I
external
associated with the SCL and SDA pins do not
reflect the actual digital logic levels on the pins.
Work around
If the SDA and/or SCL pins need to be polled,
these pins should be connected to other port pins
in order to be read correctly. This issue does not
affect the operation of the I
Affected Silicon Revisions
A2
A2
A2
mode) with pre/post-decrement
X
X
X
A3
A3
A3
X
X
X
than
2
interrupt
C module enabled, the port bits and
2
2
2
C
C
C module is configured as a 10-bit
A4
A4
A4
X
X
X
0x02;
© 2010 Microchip Technology Inc.
A5
A5
A5
X
X
X
input
however,
2
C module.
functions
the
(if
module
any)