DSPIC33FJ16GS504-E/ML Microchip Technology, DSPIC33FJ16GS504-E/ML Datasheet - Page 217
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DSPIC33FJ16GS504-E/ML
Manufacturer Part Number
DSPIC33FJ16GS504-E/ML
Description
16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ06GS101-ISO.pdf
(346 pages)
2.DSPIC33FJ06GS101-ISO.pdf
(18 pages)
3.DSPIC33FJ06GS101-ISO.pdf
(16 pages)
Specifications of DSPIC33FJ16GS504-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Package
44QFN EP
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
35
Interface Type
I2C/SPI/UART
On-chip Adc
12-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ16GS504-E/ML
Manufacturer:
MICROCHIP
Quantity:
12 000
- DSPIC33FJ06GS101-ISO PDF datasheet
- DSPIC33FJ06GS101-ISO PDF datasheet #2
- DSPIC33FJ06GS101-ISO PDF datasheet #3
- Current page: 217 of 346
- Download datasheet (6Mb)
REGISTER 15-18: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-3
bit 2-0
R/W-0
R/W-0
PHR
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger LEB counter
0 = LEB ignores rising edge of PWMxH
PHF: PWMH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger LEB counter
0 = LEB ignores falling edge of PWMxH
PLR: PWML Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger LEB counter
0 = LEB ignores rising edge of PWMxL
PLF: PWML Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger LEB counter
0 = LEB ignores falling edge of PWMxL
FLTLEBEN: Fault Input LEB Enable bit
1 = Leading-edge blanking is applied to selected Fault input
0 = Leading-edge blanking is not applied to selected Fault input
CLLEBEN: Current-Limit LEB Enable bit
1 = Leading-edge blanking is applied to selected current-limit input
0 = Leading-edge blanking is not applied to selected current-limit input
LEB: Leading-Edge Blanking for Current-Limit and Fault Inputs bits
Value is 8 nsec increments.
Unimplemented: Read as ‘0’
R/W-0
R/W-0
PHF
W = Writable bit
‘1’ = Bit is set
LEB<7:3>
R/W-0
R/W-0
PLR
R/W-0
R/W-0
PLF
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FLTLEBEN
R/W-0
R/W-0
CLLEBEN
R/W-0
U-0
—
x = Bit is unknown
R/W-0
U-0
—
LEB<9:8>
DS70318D-page 215
R/W-0
U-0
—
bit 8
bit 0
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