DSPIC33FJ16GS504T-I/PT Microchip Technology, DSPIC33FJ16GS504T-I/PT Datasheet - Page 95
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DSPIC33FJ16GS504T-I/PT
Manufacturer Part Number
DSPIC33FJ16GS504T-I/PT
Description
16 Bit MCU/DSP 40MIPS 16 KB FLASH SMPS 44 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ06GS101-ISO.pdf
(346 pages)
2.DSPIC33FJ06GS101-ISO.pdf
(18 pages)
3.DSPIC33FJ06GS101-ISO.pdf
(16 pages)
Specifications of DSPIC33FJ16GS504T-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ16GS504T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ06GS101-ISO PDF datasheet
- DSPIC33FJ06GS101-ISO PDF datasheet #2
- DSPIC33FJ06GS101-ISO PDF datasheet #3
- Current page: 95 of 346
- Download datasheet (6Mb)
FIGURE 6-3:
6.3
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to Section 24.0 “Electrical Characteristics” for
minimum pulse width specifications. The external
Reset (MCLR) pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.3.0.1
Many systems have external supervisory circuits that
generate Reset signals to reset multiple devices in the
system. This external Reset signal can be directly
connected to the MCLR pin to reset the device when
the rest of system is reset.
6.3.0.2
When using the internal power supervisory circuit to
reset the device, the external Reset pin (MCLR) should
be tied directly or resistively to V
MCLR pin will not be used to generate a Reset. The
external Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.4
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not
re-initialize the clock. The clock source in effect prior to
© 2009 Microchip Technology Inc.
External Reset (EXTR)
Software RESET Instruction (SWR)
EXTERNAL SUPERVISORY
CIRCUIT
INTERNAL SUPERVISORY CIRCUIT
SYSRST
SYSRST
SYSRST
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
V
V
V
DD
DD
DD
BROWN-OUT SITUATIONS
V
DD
dips before PWRT expires
DD
. In this case, the
Preliminary
T
BOR
the RESET instruction will remain. SYSRST is released
at the next instruction cycle and the Reset vector fetch
will commence.
The Software Reset (SWR) flag (instruction) in the
Reset Control (RCON<6>) register is set to indicate
the software Reset.
6.5
Whenever a Watchdog time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out (WDTO) flag in the
Reset Control (RCON<4>) register is set to indicate
the
“Watchdog Timer (WDT)” for more information on
Watchdog Reset.
6.6
If a lower priority hard trap occurs while a higher
priority trap is being processed, a hard Trap Conflict
Reset occurs. The hard traps include exceptions of pri-
ority level 13 through level 15, inclusive. The address
error (level 13) and oscillator error (level 14) traps fall
into this category.
The Trap Reset (TRAPR) flag in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interrupt Controller” for
more information on Trap Conflict Resets.
+ T
T
T
PWRT
BOR
BOR
Watchdog
Watchdog Time-out Reset (WDTO)
Trap Conflict Reset
+ T
+ T
PWRT
PWRT
Reset.
Refer
V
V
V
to
DS70318D-page 93
BOR
BOR
BOR
Section 21.4
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