DSPIC33FJ16MC101-E/SS Microchip Technology, DSPIC33FJ16MC101-E/SS Datasheet - Page 233
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DSPIC33FJ16MC101-E/SS
Manufacturer Part Number
DSPIC33FJ16MC101-E/SS
Description
16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 20 SSOP .209in TUB
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ16GP101-IP.pdf
(322 pages)
Specifications of DSPIC33FJ16MC101-E/SS
Processor Series
dsPIC33F
Core
dsPIC
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Interface Type
SPI, I2C, UART, JTAG
Number Of Programmable I/os
35
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Core Processor
dsPIC
Core Size
16-Bit
Speed
16 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
Number Of I /o
15
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP (0.209", 5.30mm Width)
Lead Free Status / Rohs Status
Details
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- Download datasheet (5Mb)
23.4
For
dsPIC33FJ16MC101/102 devices, the WDT is driven
by the LPRC oscillator. When the WDT is enabled, the
clock source is also enabled.
23.4.1
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler than can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (T
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the selec-
tion of 16 settings, from 1:1 to 1:32,768. Using the pres-
caler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT, prescaler, and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
• When a PWRSAV instruction is executed
• When the device exits Sleep or Idle mode to
• By a CLRWDT instruction during normal execution
FIGURE 23-2:
© 2011 Microchip Technology Inc.
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
SWDTEN
FWDTEN
LPRC Clock
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
(i.e., Sleep or Idle mode is entered)
resume normal operation
Note:
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
Watchdog Timer (WDT)
PRESCALER/POSTSCALER
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
dsPIC33FJ16GP101/102
WINDIS
WDT BLOCK DIAGRAM
WDT
) of 1 ms in 5-bit mode, or
(divide by N1)
WDTPRE
Prescaler
RS
WDT Window Select
and
Preliminary
Watchdog Timer
RS
23.4.2
If the WDT is enabled, it will continue to run during Sleep
or Idle modes. When the WDT time-out occurs, the
device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE bits
(RCON<3> and RCON<2>, respectively) will need to be
cleared in software after the device wakes up.
23.4.3
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN con-
trol bit is cleared on any device Reset. The software
WDT option allows the user application to enable the
WDT for critical code segments and disable the WDT
during non-critical segments for maximum power
savings.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
WDTPOST<3:0>
(divide by N2)
Note:
Postscaler
CLRWDT Instruction
SLEEP AND IDLE MODES
ENABLING WDT
If the WINDIS bit (FWDT<6>) is cleared,
the CLRWDT instruction should be executed
by the application software only during the
last 1/4 of the WDT period. This CLRWDT
window can be determined by using a timer.
If a CLRWDT instruction is executed before
this window, a WDT Reset occurs.
Sleep/Idle
1
0
DS70652C-page 233
WDT
Wake-up
WDT
Reset
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