DSPIC33FJ16MC102-E/SP Microchip Technology, DSPIC33FJ16MC102-E/SP Datasheet - Page 93

• Manufacturer Part Number: DSPIC33FJ16MC102-E/SP
• Description: 16-bit Motor Control DSC Family, 16 MIPS, 16KB Flash, 1KB RAM 28 SPDIP .300in TU
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16MC102-E/SP

• Processor Series: dsPIC33F
• Core: dsPIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Interface Type: SPI, I2C, UART, JTAG
• Number Of Programmable I/os: 35
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 16 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 21
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Details

REGISTER 7-12:
REGISTER 7-13:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-6
bit 5
bit 4-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-10
bit 9
bit 8-0
dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
FLTA1IE
R/W-0
U-0
U-0
U-0
—
—
—
Unimplemented: Read as ‘0’
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
FLTA1IE: PWM1 Fault A Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
RTCCIE: RTCC Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
PWM1IE: PWM1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
RTCCIE
R/W-0
U-0
U-0
U-0
—
—
—
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
‘1’ = Bit is set
‘1’ = Bit is set
W = Writable bit
W = Writable bit
R/W-0
IC3IE
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
U-0
Preliminary
—
—
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
U-0
U-0
U-0
—
—
—
—
U-0
U-0
U-0
U-0
—
—
—
—
x = Bit is unknown
x = Bit is unknown
PWM1IE
R/W-0
U-0
U-0
U-0
—
—
—
DS70652C-page 93
U-0
U-0
U-0
U-0
—
—
—
—
bit 8
bit 0
bit 8
bit 0