DSPIC33FJ256MC510T-I/PT Microchip Technology, DSPIC33FJ256MC510T-I/PT Datasheet - Page 121

• Manufacturer Part Number: DSPIC33FJ256MC510T-I/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,100PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ256MC510T-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 7-22:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-12
bit 11
bit 10-8
bit 7
bit 6-4
bit 3
bit 2-0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
Unimplemented: Read as ‘0’
U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
Unimplemented: Read as ‘0’
INT2IP<2:0>: External Interrupt 2 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
Unimplemented: Read as ‘0’
T5IP<2:0>: Timer5 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
R/W-1
R/W-1
IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U2TXIP<2:0>
INT2IP<2:0>
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
dsPIC33FJXXXMCX06/X08/X10
R/W-0
R/W-0
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
U-0
U-0
—
—
R/W-1
R/W-1
U2RXIP<2:0>
x = Bit is unknown
T5IP<2:0>
R/W-0
R/W-0
DS70287C-page 119
R/W-0
R/W-0
bit 8
bit 0