DSPIC33FJ32GP204T-I/PT Microchip Technology, DSPIC33FJ32GP204T-I/PT Datasheet - Page 278
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DSPIC33FJ32GP204T-I/PT
Manufacturer Part Number
DSPIC33FJ32GP204T-I/PT
Description
16-bit DSC, 32KB Flash,40 MIPS,nanoWatt 44 TQFP 10x10x1mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
2.DSPIC33FJ16GP304-IPT.pdf
(284 pages)
3.DSPIC33FJ16GP304-IPT.pdf
(8 pages)
4.DSPIC33FJ16GP304-IPT.pdf
(14 pages)
5.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
Specifications of DSPIC33FJ32GP204T-I/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ32GP204T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32GP204T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
I
In-Circuit Debugger ........................................................... 189
In-Circuit Emulation........................................................... 183
In-Circuit Serial Programming (ICSP) ....................... 183, 189
Input Capture
Input Change Notification.................................................. 114
Instruction Addressing Modes............................................. 47
Instruction Set
Instruction-Based Power-Saving Modes ........................... 109
Internal RC Oscillator
Internet Address................................................................ 281
Interrupt Control and Status Registers................................ 75
Interrupt Setup Procedures ................................................. 97
Interrupt Vector Table (IVT) ................................................ 71
Interrupts Coincident with Power Save Instructions.......... 110
J
JTAG Boundary Scan Interface ........................................ 183
M
Memory Organization.......................................................... 31
Microchip Internet Web Site .............................................. 281
Modulo Addressing ............................................................. 49
MPLAB ASM30 Assembler, Linker, Librarian ................... 200
MPLAB Integrated Development Environment Software .. 199
MPLAB PM3 Device Programmer..................................... 202
MPLAB REAL ICE In-Circuit Emulator System................. 201
MPLINK Object Linker/MPLIB Object Librarian ................ 200
N
NVM Module
O
Open-Drain Configuration ................................................. 114
Output Compare................................................................ 145
P
Packaging ......................................................................... 257
DS70290G-page 278
2
C Module
I2C1 Register Map ...................................................... 40
Registers ................................................................... 144
File Register Instructions ............................................ 47
Fundamental Modes Supported.................................. 48
MAC Instructions......................................................... 48
MCU Instructions ........................................................ 47
Move and Accumulator Instructions ............................ 48
Other Instructions........................................................ 48
Overview ................................................................... 194
Summary................................................................... 191
Idle ............................................................................ 110
Sleep ......................................................................... 109
Use with WDT ........................................................... 187
IECx ............................................................................ 75
IFSx............................................................................. 75
INTCON1 .................................................................... 75
INTCON2 .................................................................... 75
IPCx ............................................................................ 75
Initialization ................................................................. 97
Interrupt Disable.......................................................... 97
Interrupt Service Routine ............................................ 97
Trap Service Routine .................................................. 97
Applicability ................................................................. 50
Operation Example ..................................................... 49
Start and End Address ................................................ 49
W Address Register Selection .................................... 49
Register Map............................................................... 46
Registers ................................................................... 147
Peripheral Module Disable (PMD) .................................... 110
Pinout I/O Descriptions (table)............................................ 13
PMD Module
PORTA
PORTB
Power-on Reset (POR)....................................................... 68
Power-Saving Features .................................................... 109
Program Address Space..................................................... 31
Program Memory
R
Reader Response............................................................. 282
Registers
Details....................................................................... 259
Marking ............................................................. 257, 258
Register Map .............................................................. 46
Register Map .............................................................. 45
Register Map .............................................................. 45
Clock Frequency and Switching ............................... 109
Construction ............................................................... 52
Data Access from Program Memory Using
Data Access from Program Memory Using
Data Access from, Address Generation ..................... 53
Memory Map............................................................... 31
Table Read Instructions
Visibility Operation ...................................................... 55
Interrupt Vector ........................................................... 32
Organization ............................................................... 32
Reset Vector ............................................................... 32
AD1CHS0 (ADC1 Input Channel 0 Select ................ 179
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 177
AD1CON1 (ADC1 Control 1) .................................... 173
AD1CON2 (ADC1 Control 2) .................................... 175
AD1CON3 (ADC1 Control 3) .................................... 176
AD1CSSL (ADC1 Input Scan Select Low)................ 181
AD1PCFGL (ADC1 Port Configuration Low) ............ 181
CLKDIV (Clock Divisor) ............................................ 104
CORCON (Core Control) ...................................... 24, 76
I2CxCON (I2Cx Control) ........................................... 157
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 161
I2CxSTAT (I2Cx Status) ........................................... 159
ICxCON (Input Capture x Control)............................ 144
IEC0 (Interrupt Enable Control 0) ................... 84, 86, 87
IFS0 (Interrupt Flag Status 0) ..................................... 80
IFS1 (Interrupt Flag Status 1) ..................................... 82
IFS4 (Interrupt Flag Status 4) ..................................... 83
INTCON1 (Interrupt Control 1).................................... 77
INTCON2 (Interrupt Control 2).................................... 79
INTTREG Interrupt Control and Status Register ........ 96
IPC0 (Interrupt Priority Control 0) ............................... 88
IPC1 (Interrupt Priority Control 1) ............................... 89
IPC16 (Interrupt Priority Control 16) ........................... 95
IPC2 (Interrupt Priority Control 2) ............................... 90
IPC3 (Interrupt Priority Control 3) ............................... 91
IPC4 (Interrupt Priority Control 4) ............................... 92
IPC5 (Interrupt Priority Control 5) ............................... 93
IPC7 (Interrupt Priority Control 7) ............................... 94
NVMCOM (Flash Memory Control)....................... 59, 60
OCxCON (Output Compare x Control) ..................... 147
OSCCON (Oscillator Control) ................................... 102
OSCTUN (FRC Oscillator Tuning)............................ 107
PLLFBD (PLL Feedback Divisor).............................. 106
Program Space Visibility..................................... 55
Table Instructions ............................................... 54
TBLRDH ............................................................. 54
TBLRDL.............................................................. 54
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