DSPIC33FJ32GS406-E/PT Microchip Technology, DSPIC33FJ32GS406-E/PT Datasheet - Page 275

16 Bit MCU/DSP 40MIPS 32KB FLASH 64 TQFP 10x10x1mm TRAY

DSPIC33FJ32GS406-E/PT

Manufacturer Part Number
DSPIC33FJ32GS406-E/PT
Description
16 Bit MCU/DSP 40MIPS 32KB FLASH 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ32GS406-E/PT

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SCI, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, QEI, POR, PWM, WDT
Number Of I /o
58
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ32GS406-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
REGISTER 20-1:
 2010 Microchip Technology Inc.
bit 4
bit 3
bit 2-1
bit 0
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
2: This feature is only available for the 16x BRG mode (BRGH = 0).
information on enabling the UART module for receive or transmit operation. That section of the manual is
available on the Microchip web site, www.microchip.com.
URXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
UxMODE: UART
x
MODE REGISTER (CONTINUED)
Preliminary
DS70591C-page 275

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