DSPIC33FJ32MC204-E/ML Microchip Technology, DSPIC33FJ32MC204-E/ML Datasheet - Page 3
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DSPIC33FJ32MC204-E/ML
Manufacturer Part Number
DSPIC33FJ32MC204-E/ML
Description
16-bit DSC, 32KB Flash,Motor,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(320 pages)
2.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
3.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
Specifications of DSPIC33FJ32MC204-E/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Programming
PGEC3/
Module
PGED3
UART
PWM
PWM
CPU
ADC
Pins
QEI
QEI
QEI
I
I
I
All
2
2
2
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
Programming
Accumulation
Accumulation
Consumption
SILICON ISSUE SUMMARY (CONTINUED)
Debug Mode
DOZE Mode
Timer Gated
Timer Gated
Addressing
Generation
Instruction
Character
Operation
Interrupts
Feature
in Sleep
Current
Device
150ºC
Break
10-bit
Mode
Mode
Mode
EXCH
—
—
Number
Item
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
With the I
external Interrupt Input functions (if any) associated
with SCL and SDA pins will not reflect the actual
digital logic levels on the pins.
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register, on address match if the Least
Significant bits (LSbs) of the address are the same
as the 7-bit reserved addresses.
After the ACKSTAT bit is set when receiving a NACK,
it may be cleared by the reception of a Start or Stop
bit.
The EXCH instruction does not execute correctly.
PTMR does not keep counting down after halting
code execution in Debug mode.
The Motor Control PWM module generates more
interrupts than expected when DOZE mode is used
and the output postscaler value is different than 1:1.
The QEI module does not generate an interrupt in a
particular overflow condition.
When using the PGEC3/PGED3 pins for device
programming, the programming time may be slower
as compared to other available PGECx/PGEDx pin
pairs.
The UART module will not generate back-to-back
Break characters.
When Timer Gated Accumulation is enabled, the QEI
does not generate an interrupt on every falling edge.
When Timer Gated Accumulation is enabled, and an
external signal is applied, the POSCNT increments
and generates an interrupt after a match with
MAXCNT.
If the ADC module is in an enabled state when the
device enters Sleep Mode, the power-down current
(I
specifications.
These revisions of silicon only support 140ºC
operation instead of 150ºC for Hi-Temp operating
temperature.
PD
) of the device may exceed the device data sheet
2
C module enabled, the PORT bits and
Issue Summary
A2 A3 A4 A5 A6
X
X
X
X
X
X
X
X
X
X
X
X
X
Revisions
X
X
X
X
X
X
X
X
X
X
X
X
X
DS80463E-page 3
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X
X
X
X
X