DSPIC33FJ64MC706A-I/MR Microchip Technology, DSPIC33FJ64MC706A-I/MR Datasheet - Page 2

• Manufacturer Part Number: DSPIC33FJ64MC706A-I/MR
• Description: 16 Bit MCU/DSP 40MIPS 64KB FLASH 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64MC706A-I/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 2:
DS80464D-page 2
Operations
Note 1:
Regulator
Module
Internal
Voltage
ECAN
ECAN
UART
UART
UART
UART
I
CPU
PSV
2
QEI
QEI
SPI
SPI
I
I
I
I/O
C™
2
2
2
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Transmission
Accumulation
Accumulation
Frame Mode
Timer Gated
Timer Gated
Sleep Mode
High-Speed
Addressing
Addressing
Addressing
Generation
Instruction
SDO1 Pin
Operation
Character
Interrupts
SILICON ISSUE SUMMARY
IR Mode
Transmit
Queuing
Feature
Break
Mode
10-bit
Mode
10-bit
Mode
10-bit
Mode
Mode
Mode
EXCH
I
—
—
PD
Number
Item
10.
11.
12.
13.
14.
15.
16.
17.
18.
1.
2.
3.
4.
5.
6.
7.
8.
9.
The WAKIF bit in the CxINTF register cannot be cleared by
software instruction after the device is interrupted from Sleep
due to activity on the CAN bus.
The 16x baud clock signal on the BCLK pin is present only
when the module is transmitting.
When the UART is in 4x mode (BRGH = 1) and using two
Stop bits (STSEL = 1), it may sample the first Stop bit instead
of the second one.
The UART error interrupt may not occur, or may occur at an
incorrect time, if multiple errors occur during a short period of
time.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
After the ACKSTAT bit is set when receiving a NACK, it may
be cleared by the reception of a Start or Stop bit.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Significant
bits (LSbs) of the address are the same as the 7-bit reserved
addresses.
When the I
address of 0x102, the I2CxRCV register content for the lower
address byte is 0x01 rather than 0x02.
In framed SPI mode, when the FRMDLY bit (SPIxCON2<1>)
is cleared and SMP bit (SPIxCON1<9>) is cleared, frame sync
pulses do not get generated.
When the VREGS bit (RCON<8>) is set to a logic ‘0’, device
may Reset and higher sleep current may be observed.
An address error trap occurs in certain addressing modes
when accessing the first four bytes of any PSV page.
The EXCH instruction does not execute correctly.
Writing to the SPIxBUF register as soon as TBF bit is cleared
will cause SPI module to ignore written data.
ECAN module may not transmit Buffer 0 data if Buffer 1 data
is queued for transmission first.
The UART module will not generate back-to-back Break
characters.
When Timer Gated Accumulation is enabled, the QEI does
not generate an interrupt on every falling edge.
When Timer Gated Accumulation is enabled, and an external
signal is applied, the POSCNT increments and generates an
interrupt after a match with MAXCNT.
SDO1 pin may toggle while device is being programmed via
PGECx/PGEDx pin pairs.
2
2
C module is configured for 10-bit addressing using
C module is configured as a 10-bit slave with an
Issue Summary
2
© 2010 Microchip Technology Inc.
C devices, the
Revisions
A3
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)