DSPIC33FJ64MC802-H/SO Microchip Technology, DSPIC33FJ64MC802-H/SO Datasheet - Page 113
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DSPIC33FJ64MC802-H/SO
Manufacturer Part Number
DSPIC33FJ64MC802-H/SO
Description
16-bit DSC, 64KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
Specifications of DSPIC33FJ64MC802-H/SO
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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REGISTER 7-14:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-12
bit 11
bit 10
bit 9
bit 8-7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
DAC1LIE
R/W-0
U-0
—
2:
(2)
Interrupts are disabled on devices without ECAN™ modules.
Interrupts are disabled on devices without Audio DAC modules.
DAC1LIE: DAC Left Channel Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DAC1RIE: DAC Right Channel Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
QEI2IE: QEI2 Event Interrupt Flag Status bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
FLTA2IE: PWM2 Fault A Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
PWM2IE: PWM2 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit
1 = Interrupt request occurred
0 = Interrupt request not occurred
DMA7IE: DMA Channel 7 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DMA6IE: DMA Channel 6 Data Transfer Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
CRCIE: CRC Generator Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U2EIE: UART2 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
U1EIE: UART1 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
Unimplemented: Read as ‘0’
DAC1RIE
C1TXIE
R/W-0
R/W-0
IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
(1)
(2)
‘1’ = Bit is set
W = Writable bit
DMA7IE
R/W-0
U-0
—
DMA6IE
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
QEI2IE
CRCIE
R/W-0
R/W-0
(2)
(2)
FLTA2IE
(1)
U2EIE
R/W-0
R/W-0
x = Bit is unknown
PWM2IE
U1EIE
R/W-0
R/W-0
DS70291E-page 113
U-0
U-0
—
—
bit 8
bit 0
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