EPF6010ATC100-2N Altera, EPF6010ATC100-2N Datasheet - Page 26
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EPF6010ATC100-2N
Manufacturer Part Number
EPF6010ATC100-2N
Description
FLEX 6000
Manufacturer
Altera
Datasheet
1.EPF6010ATC100-2N.pdf
(52 pages)
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FLEX 6000 Programmable Logic Device Family Data Sheet
Output
Configuration
26
Figure 15. SameFrame Pin-Out Example
Table 6
feature.
This section discusses slew-rate control, the MultiVolt I/O interface,
power sequencing, and hot-socketing for FLEX 6000 devices.
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew-rate that can
be configured for low-noise or high-speed performance. A slower
slew-rate reduces system noise and adds a maximum delay of 6.8 ns. The
fast slew-rate should be used for speed-critical outputs in systems that are
adequately protected against noise. Designers can specify the slew-rate on
a pin-by-pin basis during design entry or assign a default slew rate to all
pins on a device-wide basis. The slew-rate setting affects only the falling
edge of the output.
Table 6. 3.3-V FLEX 6000 Devices with SameFrame Pin-Outs
100-Pin FineLine BGA Package
EPF6016A
EPF6024A
lists the 3.3-V FLEX 6000 devices with the SameFrame pin-out
Device
(Reduced I/O Count or
Logic Requirements)
Designed for 256-Pin FineLine BGA Package
FineLine
100-Pin
BGA
100-Pin FineLine BGA
Printed Circuit Board
v
256-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
FineLine
256-Pin
256-Pin FineLine BGA
BGA
Altera Corporation
v
v