EPM7064STC44-6 Altera, EPM7064STC44-6 Datasheet - Page 18
EPM7064STC44-6
Manufacturer Part Number
EPM7064STC44-6
Description
MAX 7000/S/AE/B
Manufacturer
Altera
Datasheet
1.EPM7064STC44-6.pdf
(66 pages)
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MAX 7000 Programmable Logic Device Family Data Sheet
18
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
■
■
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000S Device
The time required to program a single MAX 7000S device in-system can
be calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 7000S device
can be calculated from the following formula:
where: t
t PROG
t
VER
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t PPULSE
PROG
PPULSE
VER
VPULSE
PTCK
VTCK
+
+
Cycle
--------------------------------
Cycle
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
TCK
f
TCK
VTCK
verify the EEPROM cells
PTCK
Altera Corporation