KSZ8842-16MBLI Micrel Inc, KSZ8842-16MBLI Datasheet - Page 61

• Manufacturer Part Number: KSZ8842-16MBLI
• Description: 2-Port Ethernet Switch + Generic (8, 16-Bit) Bus Interface (I-Temp)
• Manufacturer: Micrel Inc

Specifications of KSZ8842-16MBLI

• Controller Type: Ethernet Switch Controller
• Interface: PCI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Industrial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3504

Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR
This register contains the user defined QMU RX Queue high watermark configuration bit as below.
Bank 0 Bus Error Status Register (0x06): BESR
This register flags the different kinds of errors on the host bus.
Bank 0 Bus Burst Length Register (0x08): BBLR
Before the burst can be sent, the burst length needs to be programmed.
Micrel, Inc.
Bit
15-13
12
11-0
Bit
15
14-11
10
9-0
Bit
15
14-12
11-0
October 2007
Default Value
0x0
0
Default Value
0
-
0
Default Value
0
0x000
0x000
0x0
0x000
R/W
RO
RW
RO
R/W
RO
RO
RO
RO
R/W
RO
RW
RO
Description
Reserved
QMU RX Flow Control High Watermark Configuration
0: 3 KBytes
1: 2 KBytes
Reserved
Description
IBEC Illegal Byte Enable Combination
1: illegal byte enable combination occurs. The illegal combination value can be found
from bit 14 to bit 11.
0: legal byte enable combination.
Write 1 to clear.
IBECV Illegal Byte Enable Combination Value
Bit 14: byte enable 3.
Bit 13: byte enable 2.
Bit 12: byte enable 1.
Bit 11: byte enable 0.
This value is valid only when bit 15 is set to 1.
SSAXFER Simultaneous Synchronous and Asnychronous Transfers
1: Synchronous and Asnychronous Transfers occur simultaneously.
0: normal.
Write 1 to clear.
Reserved
Description
Reserved
BRL Burst Length (for burst read and write)
000: single.
011: fixed burst read length of 4.
101: fixed burst read length of 8.
111: fixed burst read length of 16.
Reserved
61
KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9