CP3BT10G38 National Semiconductor, CP3BT10G38 Datasheet - Page 185

• Manufacturer Part Number: CP3BT10G38
• Description: IC CPU RISC W/LLC&USB 100-LQFP
• Manufacturer: National Semiconductor

Specifications of CP3BT10G38

• Applications: Connectivity Processor
• Core Processor: CR16C
• Program Memory Type: FLASH (256 kB)
• Controller Series: CP3000
• Ram Size: 10K x 8
• Interface: Bluetooth, ACCESS.bus, Audio, UART, USB, Microwire/SPI
• Number Of I /o: 37
• Voltage - Supply: 2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CP3BT10G38

27.5
All output signals are powered by the digital supply (VCC).
Table 57 summarizes the states of the output signals during
the reset state (when VCC power exists in the reset state)
and during the Power Save mode.
27.6
PB7:0
PC7:0
PG5, PG3:0
PH7:0
PI7:0
Symbol Figure
t
t
t
t
t
t
t
t
RST
X1p
X1h
X2p
X2h
t
X1l
X2l
t
IW
IH
R
a. Only when operating with an external square wave on X2CKI; otherwise a 32 kHz crystal network must be
Signals on a Pin
used between X2CKI and X2CKO. If Slow Clock is internally generated from Main Clock, it may not exceed
this given limit.
OUTPUT SIGNAL LEVELS
CLOCK AND RESET TIMING
72
72
72
72
72
72
73
73
74
74
X1 period
X1 high time, external clock
X1 low time, external clock
X2 period
X2 high time, external clock
X2 low time, external clock
Input hold time (NMI, RXD1, RXD2)
NMI Pulse Width
RESET Pulse Width
Vcc Rise Time
a
Description
Table 57 Output Pins During Reset and Power-Save
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
Reset State
(with Vcc)
Table 58 Clock and Reset Signals
Reset and NMI Input Signals
Clock Input Signals
Previous state
Previous state
Previous state
Previous state
Previous state
Power Save Mode
Rising Edge (RE) on X1 to
next RE on X1
At 2V level (Both Edges)
At 0.8V level (Both Edges)
RE on X2 to next RE on X2
At 2V level (both edges)
At 0.8V level (both edges)
After RE on CLK
NMI Falling Edge (FE) to
RE
RESET FE to RE
0.1 Vcc to 0.9 Vcc
185
The RESET and NMI input pins are active during the Power
Save mode. In order to guarantee that the Power Save cur-
rent not exceed 1 mA, these inputs must be driven to a volt-
age lower than 0.5V or higher than VCC - 0.5V. An input
voltage between 0.5V and (VCC - 0.5V) may result in power
consumption exceeding 1 mA.
Reference
I/O ports will maintain their values when
entering power-save mode
(0.5 Tclk) - 500
(0.5 Tclk) - 500
(0.5 Tclk) - 5
(0.5 Tclk) - 5
Min (ns)
10,000
83.33
100
20
Comments
0
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Max (ns)
83.33