MT9P401I12STC Aptina LLC, MT9P401I12STC Datasheet
MT9P401I12STC
Specifications of MT9P401I12STC
MT9P401I12STC
Q3412742
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MT9P401I12STC Summary of contents
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... Cellular phones • PDAs Ordering Information Table 1: Available Part Numbers Part Number MT9P401I12STC PDF: 09005aef82acb06f/Source: 09005aef81a4a477 MT9P401_DS_1 - Rev. B 9/07 EN Products and specifications discussed herein are subject to change by Micron without notice. Micron Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image Sensor www ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Maintaining a Constant Frame Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Available Part Numbers ...
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General Description The MT9P401 sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. The default mode outputs a full resolution image at 15 frames per second (fps). ...
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Figure 2: Typical Configuration (Connection) From controller Master Notes resistor value of 1.5kΩ is recommended, but may be greater for slower two-wire speed. 2. All power supplies should be adequately decoupled. 3. All D Figure 3: 48-Pin iLCC ...
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Table 3: Pin Description Name Type RESET_BAR Input EXTCLK Input SCLK Input OE Input STANDBY_BAR Input TRIGGER Input S Input ADDR S I/O DATA PIXCLK Output D [11:0] Output OUT FRAME_VALID Output LINE_VALID Output STROBE Output V Supply DD V ...
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Pixel Data Format Pixel Array Structure The MT9P401 pixel array consists of a 2752-column by 2004-row matrix of pixels addressed by column and row. The address (column 0, row 0) represents the upper-right corner of the entire array, looking at ...
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Figure 4: Pixel Array Description 50 black rows 134 black columns (2751, 2003) Figure 5: Pixel Color Pattern Detail (Top Right Corner) row readout direction Default Readout Order By convention, the sensor core pixel array is shown with pixel (0,0) ...
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Figure 6: Imaging a Scene Sensor (rear view) Column Readout Order Output Data Format (Default Mode) The MT9P401 image data is read out in a progressive scan. Valid image data is surrounded by horizontal blanking and vertical blanking, as shown ...
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Readout Sequence Typically, the readout window is set to a region including only active pixels. The user has the option of reading out dark regions of the array, but if this is done, consideration must be given to how the ...
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Output Data Timing The output images are divided into frames, which are further divided into lines. By default, the sensor produces 1944 rows of 2592 columns each. The FV and LV signals indicate the boundaries between frames and lines, respectively. ...
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Figure 9: LV Format Options Continuous LV The timing of an entire frame is shown in Figure 10. Figure 10: Frame Timing PDF: 09005aef82acb06f/Source: 09005aef81a4a477 MT9P401_DS_2 - Rev. B 9/07 EN Micron Confidential and Proprietary MT9P401: 1/2.5-Inch 5Mp Digital Image ...
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Frame Time The pixel clock (PIXCLK) represents the time needed to sample 1 pixel from the array, and is typically equal to 1 EXTCLK period. The sensor outputs data at the maximum rate of 1 pixel per PIXCLK. One row ...
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Frame Rates at Common Resolutions Table 10 and Table 11 show examples of register settings to achieve common resolu- tions and their frame rates. Frame rates are shown both with subsampling enabled and disabled. Table 10: Standard Resolutions Frame sampling ...
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Serial Bus Description Registers are written to and read from the MT9P401 through the two-wire serial inter- face bus. The MT9P401 is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial ...
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Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. Slave Address The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 ...
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Two-Wire Serial Interface Sample Write and Read Sequences 16-Bit WRITE Sequence A typical WRITE sequence for writing 16 bits to a register is shown in Figure 11. A start bit given by the master, followed by the write address, starts ...
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Registers Register List Table 12 lists sensor registers and their default values. Table 12: Register List and Default Values 1 = read-only, always read-only, always programmable read-only, dynamic Register # Dec (Hex) ...
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Table 12: Register List and Default Values (continued read-only, always read-only, always programmable read-only, dynamic Register # Dec (Hex) Register Description R65:0(R0x041) R66:0(R0x042) R67:0(R0x043) R68:0(R0x044) R69:0(R0x045) R70:0(R0x046) R71:0(R0x047) R72:0(R0x048) R73:0(R0x049) ...
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Table 12: Register List and Default Values (continued read-only, always read-only, always programmable read-only, dynamic Register # Dec (Hex) Register Description R115:0(R0x073) R116:0(R0x074) R117:0(R0x075) R118:0(R0x076) R119:0(R0x077) R120:0(R0x078) R121:0(R0x079) R122:0(R0x07A) R123:0(R0x07B) ...
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Table 12: Register List and Default Values (continued read-only, always read-only, always programmable read-only, dynamic Register # Dec (Hex) Register Description R173:0(R0x0AD) R174:0(R0x0AE) R175:0(R0x0AF) R176:0(R0x0B0) R177:0(R0x0B1) R178:0(R0x0B2) R179:0(R0x0B3) R180:0(R0x0B4) R181:0(R0x0B5) ...
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Table 12: Register List and Default Values (continued read-only, always read-only, always programmable read-only, dynamic Register # Dec (Hex) Register Description R218:0(R0x0DA) R219:0(R0x0DB) R220:0(R0x0DC) R221:0(R0x0DD) R222:0(R0x0DE) R223:0(R0x0DF) R224:0(R0x0E0) R225:0(R0x0E1) R226:0(R0x0E2) ...
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Register Description Table 13 lists sensor register descriptions. Table 13: Register Description Reg. # Bits Default Name R0:0 15:0 0x1801 Chip Version (RO) R0x000 15:8 RO Part ID Two-digit BCD value typically derived from the reticle ID code. Legal values: ...
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Table 13: Register Description (continued) Reg. # Bits Default Name R7:0 15:0 0x1F82 Output Control (RW) R0x007 15 X Reserved 14 0x0000 Reserved 13 X Reserved 12:10 0x0007 Output_Slew_Rate Controls the slew rate on digital output pads except for PIXCLK. ...
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Table 13: Register Description (continued) Reg. # Bits Default Name R10:0 15:0 0x0000 Pixel Clock Control (RW) R0x00A 15 0x0000 Invert Pixel Clock When set, LV, FV, and D_OUT should be captured on the rising edge of PIXCLK. When clear, ...
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Table 13: Register Description (continued) Reg. # Bits Default Name R13:0 15:0 0x0000 Reset (RW) R0x00D Setting this bit will put the sensor into reset mode, which will set the sensor to its default power-up state and cause it to ...
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Table 13: Register Description (continued) Reg. # Bits Default Name R30:0 15:0 0x4006 Read Mode 1 (RW) R0x01E 15 X Reserved 14 0x0001 Reserved 13 0x0000 Reserved 12 0x0000 Reserved 11 0x0000 XOR Line Valid When set, produce a LV ...
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Table 13: Register Description (continued) Reg. # Bits Default Name R32:0 15:0 0x0040 Read Mode 2 (RW) R0x020 15 0x0000 Mirror Row When set, row readout in the active image occurs in reverse numerical order starting from (Row_Start + Row_Size). ...
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Table 13: Register Description (continued) Reg. # Bits Default Name R34:0 15:0 0x0000 Row Address Mode (RW) R0x022 15 X Reserved 14:12 0x0000 Reserved 11 X Reserved 10:8 0x0000 Reserved 7:6 X Reserved 5:4 0x0000 Row Bin The number of ...
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Table 13: Register Description (continued) Reg. # Bits Default Name R43:0 15:0 0x0008 Green1 Gain (RW) R0x02B 15 X Reserved 14:8 0x0000 Green1 Digital Gain Digital Gain for the Green1 channel minus 1 times 8. The actual digital gain is ...
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Table 13: Register Description (continued) Reg. # Bits Default Name R45:0 15:0 0x0008 Red Gain (RW) R0x02D 15 X Reserved 14:8 0x0000 Red Digital Gain Digital Gain for the Red channel minus 1 times 8. The actual digital gain is ...
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Table 13: Register Description (continued) Reg. # Bits Default Name R92:0 15:0 0x005A BLC_Tune_1 (RW) R0x05C 15:12 X Reserved 11:8 0x0000 Reserved 7:0 0x005A Reserved R93:0 15:0 0x2D13 BLC_Delta_Thresholds (RW) R0x05D 15 X Reserved 14:8 0x002D Reserved 7 X Reserved ...
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Table 13: Register Description (continued) Reg. # Bits Default Name R160:0 6:3 0x0000 Test_Pattern_Control R0x0A0 Sets the test pattern mode: 0: Color field 1: Horizontal gradient 2: Vertical gradient 3: Diagonal 4: Classic 5: Walking 1s 6: Monochrome horizontal bars ...
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Features Reset The MT9P401 may be reset by using RESET_BAR (active LOW) or the reset register. Hard Reset Assert (LOW) RESET_BAR not necessary to clock the device. All registers return to the factory defaults. When the pin is ...
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The D OUT should be captured on the falling edge of PIXCLK. The specific relationship of PIXCLK to these other outputs can be adjusted in two ways. If Invert_Pixel_Clock is set, the sense of PIXCLK is inverted from that shown ...
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MHz < 180 MHz < desirable to keep ( must be between 16 and 255, inclusive. 3. Wait 1ms to ensure that the VCO has locked. 4. Set Use_PLL (R0x10[ switch from EXTCLK ...
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These settings result in the same array layout as above, but only 22 dark rows are avail- able at the top of the array; the first eight are used in the black level algorithm, and there should be a two-row ...
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Skipping can be enabled separately for rows and columns. To enable skip mode, set either or both of Row_Skip and Column_Skip to the number of pixel pairs that should be skipped for each pair used in the output image. For ...
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Figure 17: Pixel Readout (Row Skip 2X) Figure 18: Pixel Readout (Column Skip 2X, Row Skip 2X) Binning Binning reduces resolution by combining adjacent same-color imager pixels to produce one output pixel. All of the pixels in the FOV contribute ...
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Only certain combinations of binning and skipping are allowed. These are shown in Table 14 illegal skip value is selected for a bin mode, a legal value is selected instead. Table 14: Legal Values for Column_Skip Based on ...
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Mirror Column Mirror Image By setting R0x20[14 the readout order of the columns is reversed, as shown in Figure 21. The starting color, thus Bayer pattern, is preserved when mirroring the columns. Figure 21: Six Pixels in Normal ...
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Maintaining a Constant Frame Rate Maintaining a constant frame rate while continuing to have the ability to adjust certain parameters is the desired scenario. This is not always possible, however, because register updates are synchronized to the read pointer, and ...
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Fields not identified as being frame-synchronized or affected by synchronize_changes are updated immediately after the register write is completed. The effect of these regis- ters on the next frame can be difficult to predict if they affect the shutter pointer. ...
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Image Acquisition Modes The MT9P401 supports two image acquisition modes (Shutter Types) (see “Operating Modes” on page 47), electronic rolling shutter and global reset release. Electronic Rolling Shutter The ERS modes take pictures by scanning the rows of the sensor ...
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The exposure time is calculated by determining the reset time of each pixel row (with time 0 being the start of the first row time), and subtracting it from the sample time. Under normal conditions in ERS modes, every pixel ...
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The first trigger is by default automatic, producing continuous images. If snapshot is set, the first trigger can either be a low level on the TRIGGER pin or writing a “1” to the trigger register field. If Invert_Trigger is set, ...
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Figure 24: GRR Snapshot Timing TRIGGER (a) GRR Snapshot TRIGGER (b) GRR Bulb Strobe Control To support synchronization of the exposure with external events such as a flash or mechanical shutter, the MT9P401 produces a STROBE output. By default, this ...
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The sense of the STROBE signal can be inverted by setting Invert_Strobe (R0x1E[ use strobe as a flash in snapshot modes or with mechanical shutter, ...
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Green1_Analog_Multiplier, Red_Analog_Multiplier, Blue_Analog_Multiplier, and Green2_Analog_Multiplier. These combine to form the analog gain for a given color C as shown in this equation The gain component can range from 0 to 7.875 in steps ...
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Black level calibration is normally done separately for each color channel, and different channels can be using different sample or adjustment methods at the same time. However, because both Green1 and Green2 pixels go through the same signal chain, and ...
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Classic Test Pattern When selected, a value from Test_Data will be sent through the digital pipeline instead of sampled data from the sensor. The value will alternate between Test_Data for even and odd columns. Color Field When selected, the value ...
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Spectral Characteristics Figure 26: Typical Spectral Characteristics 350 Figure 27: CRA vs. Image Height (7 deg) CRA vs. Image Height Plot ...
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Electrical Specifications Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, S shown in Figure 29 and Table 19 on page 55. Figure 29: Two-Wire Serial Bus Timing Parameters t SRTH t SCLK SCLK S ...
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I/O Timing By default, the MT9P401 launches pixel data, FV and LV with the rising edge of PIXCLK. The expectation is that the user captures D PIXCLK. See Figure 30 and Table 20 for I/O timing (AC) characteristics. Figure 30: ...
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DC Electrical Characteristics Table 20: I/O Timing Characteristics Symbol Definition f EXTCLK1 Input clock frequency t EXTCLK1 Input clock period f EXTCLK2 Input clock frequency t EXTCLK2 Input clock period t R Input clock rise time t F Input clock ...
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The DC electrical characteristics are shown in Table 21, Table 22 on page 59, and Table 23 on page 59. Table 21: DC Electrical Characteristics Symbol Definition V Core digital voltage DD V _IO I/O digital voltage DD V Analog ...
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Table 22: Power Consumption Mode Full Resolution (15 fps) Streaming Caution Stresses greater than those listed in Table 23 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these ...
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Package Dimensions Figure 31: 48-Pin iLCC Package Outline Drawing D SEATING PLANE A 7.70 0.70 47X 0.80 TYP 48 1 48X 0.40 7.70 3. 4.50 3.85 10.000 ±0.075 SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC Notes: 1. ...
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Appendix A – Power-On and Standby Timing Figure 32: Power-On and Standby Timing Diagram Power DD_ MIN 1ms PIX, AA AA_ V PLL DD_ RESET_BAR STANDBY_BAR EXTCLK MIN 10 SYSCLK cycles ...
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Revision History Rev ...