N50P111 austriamicrosystems, N50P111 Datasheet - Page 18

• Manufacturer Part Number: N50P111
• Description: SW NAV JOYSTICK MOD CONTACTLESS
• Manufacturer: austriamicrosystems
• Series: EasyPoint™r
• Type: Navigation Switch, PCB Mountr

Specifications of N50P111

• Output: Contactless Magnetic Switch
• Switch Function: 2 Axis with Select
• Actuator Type: Joystick
• Termination Style: SMD (SMT) Tab
• Operating Force: 70/180gf
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Contact Rating @ Voltage: -

EasyPoint
Datasheet - I ² C i n t e r f a c e
10.4 I²C Modes
The N50P111 supports the I²C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a
receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A
master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the
bus. The N50P111 operates as a slave on the I²C bus. Connections to the bus are made through the open-drain I/O lines SDA and the input
SCL. Clock stretching is not included.
10.4.1 Automatic Increment of Address Pointer
The N50P111 slave automatically increments the address pointer after each byte transferred. The increase of the address pointer is independent
from the address being valid or not.
10.4.2 Invalid Addresses
If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or write cycle is possible.
The address pointer is increased after each byte.
10.4.3 Reading
When reading from a wrong address, the N50P111 slave data returns all zero. The address pointer is increased after each byte. Sequential read
over the whole address range is possible including address overflow.
10.4.4 Writing
A write to a wrong address is not acknowledged by the N50P111 slave, although the address pointer is increased. When the address pointer
points to a valid address again, a successful write accessed is acknowledged. Page write over the whole address range is possible including
address overflow.
The following bus protocol has been defined:
Accordingly, the following bus conditions have been defined:
Bus Not Busy.
Both data and clock lines remain HIGH.
Start Data Transfer.
A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.
Stop Data Transfer.
A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.
Data Valid.
The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the
clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between
START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each
receiver acknowledges with a ninth bit.
Acknowledge.
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must
generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW
during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must
signal an end of READ access to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
www.austriamicrosystems.com/N50P111
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH
are interpreted as start or stop signals.
TM
N50P111
Revision 1.1
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