LT1952IGN Linear Technology, LT1952IGN Datasheet - Page 11

• Manufacturer Part Number: LT1952IGN
• Description: IC,SMPS CONTROLLER,CURRENT-MODE,SOP,16PIN,PLASTIC
• Manufacturer: Linear Technology

OPERATIO
catastrophic damage. Many converters solve this problem
by limiting the operational duty cycle of the MOSFET to
50% or less — or by using a fixed (non-adaptive) maxi-
mum duty cycle clamp with very large voltage rated
MOSFETs. The LT1952/LT1952-1 provide a volt-second
clamp to allow MOSFET duty cycles well above 50%. This
gives greater power utilization for the MOSFET, rectifiers
and transformer resulting in less space for a given power
output. In addition, the volt-second clamp allows a
reduced voltage rating on the MOSFET resulting in lower
RDS
defines a maximum duty cycle ‘guard rail’ which falls when
system input voltage increases.
The LT1952/LT1952-1 SD_V
provide a capacitorless, programmable volt-second clamp
solution. Some controllers with volt-second clamps con-
trol switch maximum duty cycle by using an external
capacitor to program maximum switch ON time. Such
techniques have a volt-second clamp inaccuracy directly
related to the error of the external capacitor/pin capaci-
tance and the error/drift of the internal oscillator. The
LT1952/LT1952-1 use simple resistor ratios to implement
a volt-second clamp without the need for an accurate
external capacitor and with an order of magnitude less
dependency on oscillator error.
An increase of voltage at the SD_V
maximum duty cycle clamp to decrease. If SD_V
resistively divided down from transformer input voltage, a
volt-second clamp is realised. To adjust the initial maxi-
mum duty cycle clamp, the SS_MAXDC pin voltage is
programmed by a resistor divider from the 2.5V V
to ground. An increase of programmed voltage on
SS_MAXDC pin provides an increase of switch maximum
duty cycle clamp.
Soft-Start
The LT1952/LT1952-1 provide true PWM soft-start by
using the SS_MAXDC pin to control soft-start timing. The
proportional relationship between SS_MAXDC voltage
and switch maximum duty cycle clamp allows the
SS_MAXDC pin to slowly ramp output voltage by ramping
the maximum switch duty cycle clamp — until switch duty
ON
for greater efficiency. The volt-second clamp
U
SEC
and SS_MAXDC pins
SEC
pin causes the
REF
SEC
pin
is
cycle clamp seamlessly meets the natural duty cycle of the
converter. A soft-start event is triggered whenever V
too low, SD_V
current threshold at OC pin is exceeded. Whenever a soft-
start event is triggered, switching at SOUT and OUT is
stopped immediately.
The SS_MAXDC pin is discharged and only released for
charging when it has fallen below it’s reset threshold of
0.45V and all faults have been removed. Increasing volt-
age on the SS_MAXDC pin above 0.8V will increase switch
maximum duty cycle. A capacitor to ground on the
SS_MAXDC pin in combination with a resistor divider
from V
Current Mode Topology (I
The LT1952/LT1952-1 current mode topology eases fre-
quency compensation requirements because the output
inductor does not contribute to phase delay in the regula-
tor loop. This current mode technique means that the error
amplifier (nonisolated applications) or the optocoupler
(isolated applications) commands current (rather than
voltage) to be delivered to the output. This makes fre-
quency compensation easier and provides faster loop
response to output load transients.
A resistor divider from the application’s output voltage
generates a voltage at the inverting FB input of the LT1952/
LT1952-1 error amplifier (or to the input of an external
optocoupler) and is compared to an accurate reference
(1.23V for LT1952/LT1952-1). The error amplifier output
(COMP) defines the input threshold (I
sense comparator. COMP voltages between 0.8V (active
threshold) and 2.5V define a maximum I
from 0mV to 220mV. By connecting I
resistor in series with the source of an external power
MOSFET, the MOSFET peak current trip point (turn off) can
be controlled by COMP level and hence by the output
voltage. An increase in output load current causing the
output voltage to fall, will cause COMP to rise, increasing
I
output. For isolated applications, the error amplifier COMP
output can be disabled to allow the optocoupler to take
control. Setting FB = V
COMP output, reducing pin current to (COMP – 0.7)/40k.
SENSE
REF
threshold, increasing the current delivered to the
, defines the soft-start timing.
SEC
is too low (UVLO), or a 107mV over-
LT1952/LT1952-1
REF
SENSE
disables the error amplifier
Pin)
SENSE
SENSE
SENSE
) of the current
to a sense
threshold
11
19521fb
IN
is