LTC2242IUP-12 Linear Technology, LTC2242IUP-12 Datasheet - Page 22

• Manufacturer Part Number: LTC2242IUP-12
• Description: IC,A/D CONVERTER,SINGLE,12-BIT,CMOS,LLCC,64PIN
• Manufacturer: Linear Technology

APPLICATIONS INFORMATION
LTC2242-12
Output Enable
The outputs may be disabled with the output enable pin,
OE. In CMOS or LVDS output modes OE high disables all
data outputs including OF and CLKOUT. The data access
and bus relinquish times are too slow to allow the outputs
to be enabled and disabled during full speed operation.
The output Hi-Z state is intended for use during long
periods of inactivity.
The Hi-Z state is not a truly open circuit; the output pins
that make an LVDS output pair have a 20k resistance be-
tween them. Therefore in the CMOS output mode, adjacent
data bits will have 20k resistance in between them, even
in the Hi-Z state.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors
have to recharge and stabilize. Connecting SHDN to V
and OE to GND results in nap mode, which typically dis-
sipates 28mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap mode all digital outputs are disabled
and enter the Hi-Z state.
GROUNDING AND BYPASSING
The LTC2242-12 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with an
internal ground plane is recommended. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particular,
care should be taken not to run any digital signal alongside
an analog signal or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the V
pins. Bypass capacitors must be located as close to the
22
DD
, OV
DD
, V
CM
, REFHA, REFHB, REFLA and REFLB
DD
and OE to V
DD
DD
pins as possible. Of particular importance are the capaci-
tors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recommended. The 2.2μF capacitor between REFHA
and REFLA can be somewhat further away. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2242-12 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
HEAT TRANSFER
Most of the heat generated by the LTC2242-12 is trans-
ferred from the die through the bottom-side exposed
pad and package leads onto the printed circuit board. For
good electrical and thermal performance, the exposed
pad should be soldered to a large grounded pad on the
PC board. It is critical that all ground pins are connected
to a ground plane of suffi cient area.
Clock Sources for Undersampling
Undersampling is especially demanding on the clock source
and the higher the input frequency, the greater the sensitivity
to clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required, a
canned oscillator from vendors such as Saronix or Vectron
can be placed close to the ADC and simply connected
directly to the ADC. If there is any distance to the ADC,
some source termination to reduce ringing that may occur
even over a fraction of an inch is advisable. You must not
allow the clock to overshoot the supplies or performance
will suffer. Do not fi lter the clock signal with a narrow band
fi lter unless you have a sinusoidal clock source, as the
rise and fall time artifacts present in typical digital clock
signals will be translated into phase noise.
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