LTC1799IS5#PBF Linear Technology, LTC1799IS5#PBF Datasheet - Page 6

• Manufacturer Part Number: LTC1799IS5#PBF
• Description: 61R9518
• Manufacturer: Linear Technology
• Type: Silicon Oscillatorr

Specifications of LTC1799IS5#PBF

• Mounting Style: Surface Mount
• Screening Level: Industrial
• Product Length (mm): 2.9mm
• Product Depth (mm): 1.75mm
• Product Height (mm): 0.9mm
• Package / Case: TSOT-23
• Frequency: 33MHz
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSOT-23
• No. Of Pins: 5
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Compliant

THEORY OF OPERATIO
LTC1799
As shown in the Block Diagram, the LTC1799’s master
oscillator is controlled by the ratio of the voltage between
the V
(I
mately 1.13V below V
bias voltage. This voltage is accurate to ±7% at a particular
input current and supply voltage (see Figure 1). The
effective input resistance is approximately 2k.
A resistor R
“locks together” the voltage (V
variation. This provides the LTC1799’s high precision. The
master oscillation frequency reduces to:
The LTC1799 is optimized for use with resistors between
10k and 200k, corresponding to master oscillator fre-
quencies between 0.5MHz and 10MHz. Accurate frequen-
cies up to 20MHz (R
voltage is greater than 4V.
To extend the output frequency range, the master oscilla-
tor signal may be divided by 1, 10 or 100 before driving
6
ƒ
RES
MO
). The voltage on the SET pin is forced to approxi-
+
=
and SET pins and the current entering the SET pin
10
MHz
1.4
1.3
1.2
1.1
1.0
0.9
0.8
Figure 1. V
SET
1
, connected between the V
•
⎛
⎜
⎝
10
R
V
SET
+
SET
k
+
= 3V
+
Ω
by the PMOS transistor and its gate
10
– V
⎞
⎟
⎠
= 5k) are attainable if the supply
V
I
SET
RES
+
= 5V
(µA)
Variation with I
+
– V
100
SET
T
A
) and current, I
U
= 25°C
1799 F01
+
1000
RES
and SET pins,
RES
,
OUT (Pin 5). The divide-by value is determined by the state
of the DIV input (Pin 4). Tie DIV to GND or drive it below
0.5V to select ÷1. This is the highest frequency range, with
the master output frequency passed directly to OUT. The
DIV pin may be floated or driven to midsupply to select
÷10, the intermediate frequency range. The lowest fre-
quency range, ÷100, is selected by tying DIV to V
driving it to within 0.4V of V
ship between R
including the overlapping frequency ranges near 100kHz
and 1MHz.
The CMOS output driver has an on resistance that is
typically less than 100Ω. In the ÷1 (high frequency) mode,
the rise and fall times are typically 7ns with a 5V supply and
11ns with a 3V supply. These times maintain a clean
square wave at 10MHz (20MHz at 5V supply). In the ÷10
and ÷100 modes, where the output frequency is much
lower, slew rate control circuitry in the output driver
increases the rise/fall times to typically 14ns for a 5V
supply and 19ns for a 3V supply. The reduced slew rate
lowers EMI (electromagnetic interference) and supply
bounce.
1000
Figure 2. R
100
10
1
1k
SET
DESIRED OUTPUT FREQUENCY (Hz)
10k
, divider setting and output frequency,
SET
÷100
vs Desired Output Frequency
100k
÷10
+
. Figure 2 shows the relation-
1M
÷1
OPERATION
ACCURATE
10M
MOST
1799 F02
100M
sn1799 1799fbs
+
or