MAX261BEWG Maxim Integrated Products, MAX261BEWG Datasheet - Page 12

• Manufacturer Part Number: MAX261BEWG
• Description: Active Filter
• Manufacturer: Maxim Integrated Products

Specifications of MAX261BEWG

• Number Of Channels: 2
• Cutoff Frequency: 57 KHz
• Supply Voltage (max): 12.6 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Supply Voltage (min): 4.74 V
• Package / Case: SOIC-24 Wide
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 3 shows a block diagram of the MAX260. Each
second-order filter section has its own clock input and
independent f
quency is a function of the filter's clock rate, 6-bit f
control word (see Table 2), and operating mode. The Q
of each section is also set by a separate programmed
input (see Table 3). This way, each half of a MAX260/
MAX261/MAX262 is tuned independently so that com-
plex filter polynomials can be realized. Equations that
convert program code numbers to f
are listed in the notes beneath Tables 2 and 3.
The clock circuitry of the MAX260/MAX261/MAX262
can operate with a crystal, resistor-capacitor (RC) net-
work, or an external clock generator as shown in Figure
4. If an RC oscillator is used, the clock rate, f
nally equals 0.45/RC.
Microprocessor Programmable
Universal Active Filters
Table 2. f
Note 1: For the MAX260/MAX261, f
Note 2: For the MAX262, f
Note 3: In mode 2, all f
12
MODES 1,3,4
______________________________________________________________________________________
172.79
174.36
175.93
177.50
179.07
180.64
182.21
183.78
185.35
186.92
188.49
190.07
191.64
193.21
194.78
196.35
197.92
199.49
MAX260/MAX261 f
MAX260/MAX261
CLK
0
and Q control. The actual center fre-
/f
0
Oscillator and Clock Inputs
CLK
MODE 2
Program Selection Table (continued)
122.18
123.29
124.40
125.51
126.62
127.73
128.84
129.96
131.07
132.18
133.29
134.40
135.51
136.62
137.73
138.84
139.95
141.06
Detailed Description
CLK
/f
CLK
0
ratios are divided by √2. The functions are then:
f CLK /f 0 RATIO
/f
f
/f
0
0
0
= (26 s N)π / 2 in modes 1, 3, and 4, where N varies 0 to 63.
= 1.11072 (64 + N), MAX262 f
and Q Programming
CLK
/f
MODES 1,3,4
0
CLK
= (64 + N)π / 2 in modes 1, 3, and 4, where N varies from 0 to 63.
113.10
114.66
117.81
119.38
120.95
122.52
124.09
125.66
127.23
128.81
130.38
131.95
133.52
135.09
136.66
138.23
139.80
11624
/f
0
and Q values
CLK
MAX262
, nomi-
MODE 2
0
79.97
81.08
82.19
83.30
84.41
85.53
86.64
87.75
88.86
89.97
91.08
92.19
93.30
94.41
95.52
96.63
97.74
98.85
CLK
/f
0
The duty cycle of the clock at CLK
portant because the input is internally divided by 2 to
generate the sampling clock for each filter section. It is
important to note that this internal division also halves
the sample rate when considering aliasing and other
sampled system phenomenon.
f
program memory. The memory contents are updated
by writing to addresses selected by A0–A3. D0, and D1
are the data inputs. A map of the memory locations is
shown in Table 4. Data is stored in the selected
address on the rising edge of WR. Address and data
inputs are TTL and CMOS compatible when the filter is
powered from ±5V. With other power supply voltages,
CMOS logic levels should be used. Interface timing is
shown in Figure 5. Note: Clock inputs CLK
have no relation to the digital interface. They control the
switched-capacitor filter sample rate only.
Some noise may be generated on the filter outputs by
transitions at the logic inputs. If this is objectionable,
0
= 1.11072 (26 + N)
, Q, and mode-selection data are stored in internal
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
N
F5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
F4
PROGRAM CODE
Microprocessor Interface
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
F3
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A
F2
and CLK
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A
F1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
and CLK
B
is unim-
F0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
B