CS5342-CZZR Cirrus Logic Inc, CS5342-CZZR Datasheet
CS5342-CZZR
Specifications of CS5342-CZZR
Related parts for CS5342-CZZR
CS5342-CZZR Summary of contents
Page 1
... The CS5342 uses a 5th-order, multi-bit Delta-Sigma modulator followed by digital filtering and decimation, which removes the need for an external anti-alias filter. The CS5342 is available in a 16-pin TSSOP package in Commercial grade (-10° to 70° C). The CDB5342 Cus- tomer Demonstration board is also available for device evaluation and implementation suggestions ...
Page 2
... Figure 15.Master Mode, I²S SAI ................................................................................................................ 11 Figure 16.Slave Mode, I²S SAI .................................................................................................................. 11 Figure 17.Typical Connection Diagram ..................................................................................................... 13 Figure 18.CS5342 Master Mode Clocking ................................................................................................ 15 Figure 19.Left-Justified Serial Audio Interface .......................................................................................... 16 Figure 20.I²S Serial Audio Interface .......................................................................................................... 16 Figure 21.CS5342 Recommended Analog Input Buffer ............................................................................ 17 Figure 22.CS5342 THD+N versus Frequency .......................................................................................... 18 2 CS5342 DS608F1 ...
Page 3
... LIST OF TABLES Table 1. Speed Modes and the Associated Output Sample Rates (Fs) .................................................... 14 Table 2. CS5342 Mode Control ................................................................................................................. 14 Table 3. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates ...................................... 16 DS608F1 CS5342 3 ...
Page 4
... Ambient Operating Temperature Notes: 1. This part is specified at typical analog voltages of 3.3 V and 5.0 V. See (CS5342-CZZ)” on page Quad-Speed Slave Mode, the CS5342 is only specified for operation with VA and ±5%. ABSOLUTE MAXIMUM RATINGS (GND = 0 V, All voltages with respect to ground.) Parameter DC Power Supplies: ...
Page 5
... ANALOG CHARACTERISTICS (CS5342-CZZ) Test conditions (unless otherwise specified): Input test signal kHz sine wave; measurement bandwidth kHz. Dynamic Performance for Commercial Grade Single-Speed Mode kHz Dynamic Range Total Harmonic Distortion + Noise Double-Speed Mode kHz Dynamic Range 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise ...
Page 6
... Phase Deviation @ 20 Hz Passband Ripple Filter Settling Time 7. Response is clock dependent and will scale with Fs. Note that the response plots normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 6 (Note 7) (Note 7) (Note 7) CS5342 Symbol Min Typ Max 0 - 0.4896 -0.1 - 0.035 ...
Page 7
... Figure 5. Double-Speed Stopband Rejection DS608F1 -10 0 -110 -12 0 - Figure 2. Single-Speed Stopband Rejection (detail .10 0 .51 0 .52 0 .53 0 .54 0 .55 Figure 4. Single-Speed Passband Ripple -10 0 -110 -12 0 - Figure 6. Double-Speed Stopband Rejection (detail) CS5342 .50 0 .52 0 . aliz . aliz .50 0 .52 0 . aliz . . ...
Page 8
... Figure 8. Double-Speed Passband Ripple -10 0 -110 -12 0 - 1.0 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 Figure 10. Quad-Speed Stopband Rejection (detail . .10 Figure 12. Quad-Speed Passband Ripple CS5342 . aliz aliz .13 0 . aliz DS608F1 0 .50 ...
Page 9
... Input Leakage Current DS608F1 Symbol Min Positive Analog VA 3.14 Positive Digital VD 3.14 Positive Logic VL, VL, VL,VD VL, VD VL PSRR (Note 9) Output Impedance Output Impedance Symbol (% CS5342 Note 2) Typ Max - 5.25 - 5. 25.5 - 18 180 220 - 90 107 ÷ ...
Page 10
... Symbol Min t 26 clkw -20 mslr t - sdo Single-Speed - Double-Speed - Quad-Speed - 40 t 313 sclkw stp t 5 hld t -20 slrd 40 t 208 sclkw stp t 5 hld t -20 slrd 40 t 104 sclkw stp t 5 hld t -8 slrd Table 1 on page 14 CS5342 Typ Max Unit - 1302 ...
Page 11
... Figure 15. Master Mode, I²S SAI DS608F1 LRCK input SCLK input t sdo MSB-1 SDOUT Figure 14. Slave Mode, Left-Justified SAI LRCK input SCLK input t sdo MSB MSB-1 SDOUT Figure 16. Slave Mode, I²S SAI CS5342 t sclkw t slrd t stp t hld MSB MSB-1 t sclkw t slrd t stp t hld MSB 11 ...
Page 12
... Analog Power (Input) - Positive power supply for the analog section. REFGND 14 Reference Ground (Output) - Ground reference for the internal sampling circuits. Positive Voltage Reference (Output) - Positive reference voltage for the internal FILT+ 15 sampling circuits MCLK FILT REFGND SDOUT GND AINR SCLK AINL LRCK RST Pin Description CS5342 DS608F1 ...
Page 13
... F 2 Ω 0.1 µ RST M0 M1 CS5342 A/D CONVERTER SDOUT MCLK LRCK SCLK GND Figure 17. Typical Connection Diagram CS5342 2. µ F Power Down and Mode Settings GND Ω Audio Data Processor Timing Logic and Clock Pull- for I S Capacitor value affects ...
Page 14
... APPLICATIONS 4.1 Single-, Double-, and Quad-Speed Modes The CS5342 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be de- termined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode * Quad-Speed Mode, 96x only available in Master Mode ...
Page 15
... Fs. Additionally, Quad-Speed Slave Mode is only specified for operation with a VA and ±5%. A unique feature of the CS5342 is the automatic selection of either Single-, Double- or Quad-Speed Mode when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode pins to correspond to the desired mode ...
Page 16
... Master Clock The CS5342 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is also an internal MCLK divider which is automatically activated according to the frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required. ...
Page 17
... Synchronization of Multiple Devices In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5342’s in the system. 4.8 Capacitor Size on the Reference Pin (FILT+) The CS5342 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decoupling capacitor affects the low frequency distortion performance, as shown in capacitor values used to optimize low frequency distortion performance ...
Page 18
... Single-Speed Master Mode using a 1 kHz input tone of magni- tude -1 dB Full-Scale 2.2 uF 3.3 uF 4.7 uF 5 100 uF Figure 22. CS5342 THD+N versus Frequency 18 CS5342 DS608F1 ...
Page 19
... The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS608F1 CS5342 19 ...
Page 20
... JEDEC #: MO-153 Controlling Dimension is Millimeters Symbol θ JA CS5342 1 E1 END VIEW L MILLIMETERS NOM MAX -- 1.10 -- 0.15 0.90 0.95 0.245 0.30 5.00 5.10 6.40 6.50 4.40 4.50 0.65 BSC -- 0 ...
Page 21
... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS608F1 Grade Temp Range Yes Commercial -10° to 70° www.cirrus.com. CS5342 Container Order # Tube CS5342-CZZ Tape and Reel CS5342-CZZR - - - 21 ...