WM8973LGEFL/RV Wolfson Microelectronics, WM8973LGEFL/RV Datasheet - Page 39

• Manufacturer Part Number: WM8973LGEFL/RV
• Description: Audio CODECs Stereo Codec with H/P Spkr
• Manufacturer: Wolfson Microelectronics

Specifications of WM8973LGEFL/RV

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
w
DIGITAL AUDIO INTERFACE
LINE OUTPUT
The analogue outputs, LOUT1/ROUT1 and LOUT2/ROUT2, can be used as line outputs.
Additionally, OUT3 and MONOOUT can be used as a stereo line-out by setting OUT3SW=11 (reg.
24) and ensuring the contents of registers 38 and 39 (mono-out mix) are the same as reg. 34 and 35
(left out mix). Recommended external components are shown below.
Figure 15 Recommended Circuit for Line Output
The DC blocking capacitors and the load resistance together determine the lower cut-off frequency,
f
f
Increasing the capacitance lowers f
diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage
when used improperly.
The digital audio interface is used for inputting DAC data into the WM8973L and outputting ADC data
from it. It uses five pins:
The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8973L operates as a
master, or inputs when it is a slave (see Master and Slave Mode Operation, below).
Four different audio data formats are supported:
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the
Electrical Characteristic section for timing information.
MASTER AND SLAVE MODE OPERATION
The WM8973L can be configured as either a master or slave mode device. As a master device the
WM8973L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data
transfer on ADCDAT and DACDAT. In slave mode, the WM8973L responds with data to clocks it
receives over the digital audio interface. The mode can be selected by writing to the MS bit (see
Table 23). Master and slave modes are illustrated below.
Figure 16 Master Mode
c
c
. Assuming a 10 kOhm load and C1, C2 = 1 F:
= 1 / 2 (R
ADCDAT: ADC data output
ADCLRC: ADC data alignment clock
DACDAT: DAC data input
DACLRC: DAC data alignment clock
BCLK: Bit clock, for synchronisation
Left justified
Right justified
I
DSP mode
2
S
L
+R
1
) C
1
= 1 / (2 x 10.1k
c
, improving the bass response. Smaller values of C1 and C2 will
x 1 F) = 16 Hz
Figure 17 Slave Mode
PD Rev 4.2 September 2005
WM8973L
39