WM8978GEFL/RV Wolfson Microelectronics, WM8978GEFL/RV Datasheet
WM8978GEFL/RV
Specifications of WM8978GEFL/RV
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WM8978GEFL/RV Summary of contents
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... SPKVDD Capable of driving piezo speakers Stereo speaker drive configuration Programmable preamp gain Psuedo differential inputs with common mode rejection Programmable ALC / Noise Gate in ADC path 2.5V to 3.6V (digital: 1.71V to 3.6V) Production Data, June 2009, Rev 4.4 Copyright ©2009 Wolfson Microelectronics plc ...
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WM8978 DESCRIPTION ....................................................................................................... 1 BLOCK DIAGRAM ................................................................................................. 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION ........................................................................................... 4 ORDERING INFORMATION .................................................................................. 4 PIN DESCRIPTION ................................................................................................ 5 ABSOLUTE MAXIMUM RATINGS ......................................................................... 6 RECOMMENDED OPERATING CONDITIONS ..................................................... 6 ...
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Production Data 5-BAND EQUALISER ................................................................................................ 111 APPLICATION INFORMATION .......................................................................... 115 RECOMMENDED EXTERNAL COMPONENTS ........................................................ 115 PACKAGE DIAGRAM ........................................................................................ 116 IMPORTANT NOTICE ........................................................................................ 117 ADDRESS ................................................................................................................. 117 w WM8978 PD Rev 4.4 June 2009 3 ...
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... WM8978 PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8978GEFL/V -40°C to +100°C WM8978GEFL/RV -40°C to +100°C Note: Reel quantity = 3,500 w PACKAGE MOISTURE SENSITIVITY LEVEL 32-lead QFN ( mm) (Pb-free) 32-lead QFN ( mm) (Pb-free, tape and reel) Production Data PEAK SOLDERING TEMPERATURE o MSL3 260 ...
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Production Data PIN DESCRIPTION PIN NAME 1 LIP Analogue input Analogue input 2 LIN 3 L2/GPIO2 Analogue input 4 RIP Analogue input 5 RIN Analogue input 6 R2/GPIO3 Analogue input 7 LRC Digital Input / Output 8 BCLK Digital Input ...
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WM8978 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
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Production Data ELECTRICAL CHARACTERISTICS Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T stated. PARAMETER Microphone Preamp Inputs (LIP, LIN, RIP, RIN, L2, R2) Full-scale Input Signal Level – note this changes in proportion to AVDD (Note 1) Mic PGA equivalent input noise ...
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WM8978 Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T stated. PARAMETER Automatic Level Control (ALC) Target Record Level Programmable gain Gain Hold Time (Note 3,5) Gain Ramp-Up (Decay) Time (Note 4,5) Gain Ramp-Down (Attack) Time (Note 4,5) Mute Attenuation Analogue to Digital ...
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Production Data Test Conditions DCVDD=1.8V, AVDD=DBVDD=SPKVDD= 3.3V, T stated. PARAMETER Speaker Output (LOUT2, ROUT2 with 8Ω bridge tied load, INVROUT2=1) Full scale output voltage, 0dB gain. (Note 9) Output Power Total Harmonic Distortion Signal to Noise Ratio Power Supply Rejection ...
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WM8978 TERMINOLOGY 1. Input level to RIP and LIP is limited to a maximum of -3dB or THD+N performance will be reduced. 2. Note when BEEP path is not enabled then AUXL and AUXR have the same input impedances. 3. ...
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Production Data SPEAKER OUTPUT THD VERSUS POWER w WM8978 PD Rev 4.4 June 2009 11 ...
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WM8978 POWER CONSUMPTION Typical current consumption for various scenarios is shown below. MODE Off Sleep (VREF maintained, no clocks) 2 Stereo Record (8kHz) Stereo 16Ω HP Playback (44.1kHz, quiescent) Stereo 16Ω HP Playback (44.1kHz, white noise) Stereo 16Ω HP Playback ...
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Production Data REGISTER BIT BUFDCOPEN OUT4MIXEN OUT3MIXEN PLLEN MICBEN BIASEN BUFIOEN VMIDSEL ROUT1EN LOUT1EN BOOSTENR BOOSTENL INPPGAENR INPPGAENL ADCENR ADCENL OUT4EN OUT3EN LOUT2EN ROUT2EN RMIXEN LMIXEN DACENR DACENL Table 2 AVDD Supply Current (AVDD=3.3V) w AVDD CURRENT (mA) AVDD=3.3V 0.1 ...
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WM8978 AUDIO PATHS OVERVIEW w Production Data PD Rev 4.4 June 2009 14 ...
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Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 1 System Clock Timing Requirements Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T PARAMETER System Clock Timing Information MCLK cycle time MCLK duty cycle Note 1: PLL pre-scaling and PLL N and ...
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WM8978 Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRC propagation delay from BCLK falling edge ADCDAT propagation delay from BCLK falling edge DACDAT setup time to BCLK rising edge DACDAT hold ...
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Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.8V, DBVDD = AVDD = SPKVDD = 3.3V, DGND = AGND = SPKGND = 0V, T MCLK = ...
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WM8978 CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low ...
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Production Data INTERNAL POWER ON RESET CIRCUIT Figure 6 Internal Power on Reset Circuit Schematic The WM8978 includes an internal Power-On-Reset Circuit (POR), as shown in Figure 6, which is used reset the digital logic into a default state after ...
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WM8978 Figure 8 Typical Power up Sequence where DVDD is Powered before AVDD Figure 8 shows a typical power-up sequence where DVDD comes up first. First it is assumed that DVDD is already up to specified operating voltage. When AVDD ...
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Production Data DEVICE DESCRIPTION INTRODUCTION The WM8978 is a low power audio CODEC combining a high quality stereo audio DAC and ADC, with flexible line and microphone input and output processing. Applications for this device include multimedia phones, stereo digital ...
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WM8978 OUT3 and OUT4 can be configured to provide an additional stereo lineout from the output of the DACs, the mixers or the input microphone boost stages. Alternatively OUT4 can be configured as a mono mix of left and right ...
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Production Data AUXILIARY ANALOGUE INPUTS An analogue stereo FM tuner or other auxiliary analogue input can be connected to the Line inputs of WM8978, and the stereo signal listened to via headphones, or recorded, simultaneously if required. INPUT SIGNAL PATH ...
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WM8978 The input PGAs are enabled by the IPPGAENL/R register bits. REGISTER ADDRESS R2 Power Management 2 Table 4 Input PGA Enable Register Settings REGISTER ADDRESS R44 Input Control Table 5 Input PGA Control INPUT PGA VOLUME CONTROLS The input ...
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Production Data REGISTER ADDRESS R45 Left channel input PGA volume control R46 Right channel input PGA volume control R32 ALC control 1 Table 6 Input PGA Volume Control VOLUME UPDATES Volume settings will not be applied to the PGAs until ...
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WM8978 Figure 10 Simultaneous Left and Right Volume Updates If the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in Figure 11. Figure 11 Click Noise During Volume Update In order ...
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Production Data Figure 12 Volume Update Using Zero Cross Detection If there is a long period where no zero-crossing occurs, a timeout circuit in the WM8978 will automatically update the volume. The volume updates will occur between one and two ...
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WM8978 AUXILLIARY INPUTS There are two such as stereo line inputs ‘beep’ input signal to be mixed with the outputs. The AUXL/R inputs can be used as a line input to the input BOOST stage which has ...
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Production Data REGISTER ADDRESS R47 Left channel Input BOOST control R48 Right channel Input BOOST control Table 8 Input BOOST Stage Control The BOOST stage is enabled under control of the BOOSTEN register bit. REGISTER ADDRESS R2 Power management 2 ...
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WM8978 MICROPHONE BIASING CIRCUIT The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can ...
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Production Data Figure 16 ADC Digital Filter Path The ADCs are enabled by the ADCENL/R register bit. REGISTER ADDRESS R2 Power management 2 Table 12 ADC Enable Control The polarity of the output signal can also be changed under software ...
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WM8978 REGISTER ADDRESS R14 ADC Control Table 14 ADC Enable Control HPFCUT [2:0] 000 001 010 011 100 101 110 111 Table 15 High Pass Filter Cut-off Frequencies (HPFAPP=1). Values in Hz. Note that the High Pass filter values (when ...
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Production Data PROGRAMMABLE NOTCH FILTER A programmable notch filter is provided. This filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. The coefficients must be entered in 2’s complement notation. A0 and a1 are ...
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WM8978 NOTCH FILTER WORKED EXAMPLE The following example illustrates how to calculate the a0 and a1 coefficients for a desired centre frequency and -3dB bandwidth 1000 100 48000 ...
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Production Data REGISTER ADDRESS R15 Left channel ADC Digital Volume R16 Right channel ADC Digital Volume w BIT LABEL DEFAULT 7:0 ADCVOLL 11111111 Left ADC Digital Volume Control [7:0] ( 0dB ) 0000 0000 = Digital Mute 0000 0001 = ...
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WM8978 INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) The WM8978 has an automatic PGA gain control circuit, which can function as an input peak limiter automatic level control (ALC). The Automatic Level Control (ALC) provides continuous adjustment ...
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Production Data REGISTER ADDRESS R34 (22h) ALC Control 3 w BIT LABEL DEFAULT 7:4 ALCHLD 0000 [3:0] (0ms) 8 ALCMODE 0 7:4 ALCDCY 0011 [3:0] (26ms/6dB) 0011 (5.8ms/6dB) 3:0 ALCATK 0010 [3:0] (3.3ms/6dB) 0010 (726us/6dB) WM8978 DESCRIPTION ALC hold time ...
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WM8978 REGISTER ADDRESS Table 17 ALC Control Registers When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input gain update must be made by writing to the INPPGAVOLL/R register bits. NORMAL ...
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Production Data LIMITER MODE In limiter mode, the ALC will reduce peaks that go above the threshold level, but will not increase the PGA gain beyond the starting level. The starting level is the PGA gain setting when the ALC ...
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WM8978 11. Enable input PGA – set INPPGAENR (R2[3] =1) and INPPGAENL (R2[2] =1). ATTACK AND DECAY TIMES The attack and decay times set the update times for the PGA gain. The attack time is the time constant used when ...
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Production Data LIMITER MODE ALCMODE = 1 (Limiter Mode) ALCATK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 ALCMODE = 1 (Limiter Mode) ALCDCY 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 19 ...
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WM8978 Figure 19 ALC Min/Max Gain ALCMAX 111 110 101 100 011 010 001 000 Table 21 ALC Max Gain Values ALCMIN 000 001 010 011 100 101 110 111 Table 22 ALC Min Gain Values Note that if the ...
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Production Data ALC HOLD TIME (NORMAL MODE ONLY) In Normal mode, the ALC has an adjustable hold time which sets a time delay before the ALC begins its decay phase (gain increasing). The hold time is set by the ALCHLD ...
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WM8978 Figure 21 ALC Hold Time ALCHLD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Table 24 ALC Hold Time Values w t (s) HOLD 0 2.67ms 5.34ms 10.7ms 21.4ms 42.7ms 85.4ms 171ms 342ms 684ms 1.37s Production ...
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Production Data PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ...
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WM8978 Figure 22 ALC Operation Above Noise Gate Threshold w Production Data PD Rev 4.4 June 2009 46 ...
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Production Data Figure 23 Noise Gate Operation OUTPUT SIGNAL PATH The WM8978 output signal paths consist of digital application filters, up-sampling filters, stereo Hi-Fi DACs, analogue mixers, speaker, stereo headphone and stereo line/mono/midrail output drivers. The digital filters and DAC ...
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WM8978 Figure 24 DAC Digital Filter Path The analogue outputs from the DACs can then be mixed with the aux analogue inputs and the ADC analogue inputs. The mix is fed to the output drivers for headphone (LOUT1/ROUT1), speaker (LOUT2/ROUT2) ...
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Production Data The DAC output phase defaults to non-inverted. Setting DACPOLL will invert the DAC output phase on the left channel and DACPOLR inverts the phase on the right channel. AUTO-MUTE The DAC has an auto-mute function which applies an ...
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WM8978 Figure 25 DAC Digital Limiter Operation The limiter has a programmable upper threshold which is close to 0dB. Referring to Figure 25, in normal operation (LIMBOOST=000 => limit only) signals below this threshold are unaffected by the limiter. LIMATK ...
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Production Data REGISTER ADDRESS R24 DAC digital limiter control 1 R25 DAC digital limiter control 2 w BIT LABEL DEFAULT 3:0 LIMATK 0010 7:4 LIMDCY 0011 8 LIMEN 0 3:0 LIMBOOST 0000 WM8978 DESCRIPTION Limiter Attack time (per 6dB gain ...
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WM8978 Table 29 DAC Digital Limiter Control 5-BAND GRAPHIC EQUALISER A 5-band graphic equaliser (EQ) is provided, which can be applied to the ADC or DAC path, together with 3D enhancement, under control of the EQ3DMODE register bit. REGISTER ADDRESS ...
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Production Data REGISTER ADDRESS R20 EQ Band 3 Control Table 33 EQ Band 3 Control REGISTER ADDRESS R21 EQ Band 4 Control Table 34 EQ Band 4 Control REGISTER ADDRESS R22 EQ Band 5 Gain Control Table 35 EQ Band ...
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WM8978 3D STEREO ENHANCEMENT The WM8978 has a digital 3D enhancement option to increase the perceived separation between the left and right channels. Selection of 3D for record or playback is controlled by register bit EQ3DMODE. Switching this bit from ...
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Production Data Figure 26 Left/Right Output Channel Mixers w WM8978 PD Rev 4.4 June 2009 55 ...
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WM8978 REGISTER ADDRESS R49 Output mixer control R50 Left channel output mixer control R51 Right channel output mixer control w BIT LABEL DEFAULT 5 DACR2LMIX 0 6 DACL2RMIX 0 0 DACL2LMIX 1 1 BYPL2LMIX 0 4:2 BYPLMIXVOL 000 5 AUXL2LMIX ...
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Production Data REGISTER ADDRESS R3 Power management 3 Table 38 Left and Right Output Mixer Control HEADPHONE OUTPUTS (LOUT1 AND ROUT1) The headphone outputs, LOUT1 and ROUT1 can drive a 16Ω or 32Ω headphone load, either through DC blocking capacitors, ...
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WM8978 REGISTER ADDRESS R52 LOUT1 Volume control R53 ROUT1 Volume control Table 39 OUT1 Volume Control w BIT LABEL DEFAULT 7 LOUT1ZC 0 6 LOUT1MUTE 0 5:0 LOUT1VOL 111001 8 HPVU Not latched 7 ROUT1ZC 0 6 ROUT1MUTE 0 5:0 ...
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Production Data Headphone Output using DC Blocking Capacitors: Figure 28 Recommended Headphone Output Configurations When DC blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, f response. Smaller capacitance values will diminish ...
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WM8978 Figure 29 Speaker Outputs LOUT2 and ROUT2 w Production Data PD Rev 4.4 June 2009 60 ...
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Production Data REGISTER ADDRESS R54 LOUT2 (SPK) Volume control R55 ROUT2 (SPK) Volume control Table 40 Speaker Volume Control The signal output on LOUT2/ROUT2 comes from the Left/Right Mixer circuits and can be any combination of the DAC output, the ...
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WM8978 REGISTER ADDRESS R49 Output control R1 Power management 1 Table 41 Speaker Boost Stage Control SPKBOOST Table 42 Output Boost Stage Details REGISTER ADDRESS R43 Beep control Table 43 AUXR – ROUT2 BEEP Mixer Function ZERO CROSS TIMEOUT A ...
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Production Data OUT3/OUT4 MIXERS AND OUTPUT STAGES The OUT3/OUT4 pins can provide an additional stereo line output, a mono output pseudo ground connection for headphones. There is a dedicated analogue mixer for OUT3 and one for OUT4 as ...
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WM8978 REGISTER ADDRESS R56 OUT3 mixer control R57 OUT4 mixer control Table 45 OUT3/OUT4 Mixer Registers The OUT3 and OUT4 output stages each have a selectable gain boost of 1.5x (3.52dB). When this boost is enabled the output DC level ...
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Production Data Figure 33 Outputs OUT3 and OUT4 REGISTER ADDRESS R49 Output control R1 Power management 1 Table 46 OUT3 and OUT4 Boost Stages Control OUT3BOOST/ OUT4BOOST Table 47 OUT3/OUT4 Output Boost Stage Details w BIT LABEL 3 OUT3BOOST 4 ...
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WM8978 OUTPUT PHASING The relative phases of the analogue outputs will depend upon the following factors: 1. DACPOLL and DACPOLR invert bits: Setting these bits to 1 will invert the DAC output. 2. Mixer configuration: The polarity of the signal ...
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Production Data Table 48 shows the polarities of the outputs in various configurations. Unless otherwise stated, polarity is shown with respect to left DAC output in non-inverting mode. Note that only registers relating to the mixer paths are shown here ...
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WM8978 ENABLING THE OUTPUTS Each analogue output of the WM8978 can be separately enabled or disabled. The analogue mixer associated with each output has a separate enable. All outputs are disabled by default. To save power, unused parts of the ...
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Production Data A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 35. This buffer can be enabled using the BUFIOEN register bit. If the SPKBOOST, OUT3BOOST or OUT4BOOST bits are set then the ...
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WM8978 DIGITAL AUDIO INTERFACES The audio interface has four pins: • • • • The clock signals BCLK, and LRC can be outputs when the WM8978 operates as a master, or inputs when slave (see Master and ...
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Production Data In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may ...
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WM8978 In DSP/PCM mode, the left channel MSB is available on either the 1 rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK ...
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Production Data REGISTER ADDRESS R4 Audio Interface Control Table 53 Audio Interface Control ADCLRSWAP bit controls whether the ADC data appears in the right or left phase of the LRC clock as defined for each audio format. Similarly, DACLRSWAP can ...
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WM8978 REGISTER ADDRESS R6 Clock Generation Control Table 54 Clock Control The CLKSEL bit selects the internal source of the Master clock from the PLL (CLKSEL=1) or from MCLK (CLKSEL=0). When the internal clock is switched from one source to ...
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Production Data AUDIO SAMPLE RATES The WM8978 sample rates for the ADCs and the DACs are set using the SR register bits. The cutoffs for the digital filters and the ALC attack/decay times stated are determined using these values and ...
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WM8978 Figure 41 PLL and Clock Select Circuit The PLL frequency ratio PLLN = int R PLLK = int (2 Note: The PLL is designed to operate with best performance (shortest lock time and optimum stability) when ...
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Production Data R39 PLL K Value 3 Table 57 PLL Frequency Ratio Control The PLL performs best when f are shown in Table 58. MCLK DESIRED OUTPUT (MHZ) (MHZ) (F1) 12 11.29 90.3168 12 12.288 13 11.29 90.3168 13 12.288 ...
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WM8978 REGISTER ADDRESS R5 Companding Control Table 59 Companding Control Companding involves using a piecewise linear approximation of the following equations (as set out by ITU-T G.711 standard) for data compression: μ-law (where μ=255 for the U.S. and Japan): F(x) ...
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Production Data 120 100 Figure 42 u-Law Companding 120 100 Figure 43 A-Law Companding GENERAL PURPOSE INPUT/OUTPUT The WM8978 has three dual purpose input/output pins. • • • The GPIO2 and GPIO3 functions are provided for ...
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WM8978 REGISTER ADDRESS R8 GPIO Control Table 61 CSB/GPIO Control Note: If MODE is set to 3 wire mode, CSB/GPIO1 shall be used as CSB input irrespective of the GPIO1SEL[2:] bits. Note that SLOWCLKEN must be enabled when using the ...
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Production Data The VMID_EN signal has an OR function performed with the normal VMID driver enable. If the VMID_EN signal is to have no effect to normal functionality when jack detection is enabled, it should set to 0 for all ...
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WM8978 CONTROL INTERFACE SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin determines the wire mode as shown in Table 63. The ...
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Production Data SDIN SCLK Figure 45 2-Wire Serial Control Interface In 2-wire mode the WM8978 has a fixed device address, 0011010. RESETTING THE CHIP The WM8978 can be reset by performing a write of any value to the software reset ...
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WM8978 8. Enable other outputs as required. 9. Set remaining registers. Power-up when using the output 1.5x boost stage: 1. Turn on external power supplies. Wait for supply voltage to settle. 2. Mute all analogue outputs. 3. Enable unused output ...
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Production Data Notes: 1. This step enables the internal device bias buffer and the VMID buffer for unassigned inputs/outputs. This will provide a startup reference voltage for all inputs and outputs. This will cause the inputs and outputs to ramp ...
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WM8978 Notes: 1. The analogue input pin charge time, t time is dependent upon the value of VMID decoupling capacitor and VMID pin input resistance and AVDD power supply rise time. 2. The analogue input pin discharge time, t capacitor ...
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Production Data SYMBOL t line_midrail_on t line_midrail_off t hp_midrail_on t hp__midrail_off t dacint DAC Group Delay Table 65 Typical POR Operation (typical simulated values) Notes: 1. The lineout charge time, t time is dependent upon the value of VMID decoupling ...
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WM8978 POWER MANAGEMENT SAVING POWER BY REDUCING OVERSAMPLING RATE The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x ...
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Production Data REGISTER MAP REGISTER B8 ADDR NAME B[15:9] DEC HEX 0 00 Software Reset 1 01 Power manage’t 1 BUFDCOP Power manage’t 2 ROUT1EN 3 03 Power manage’t 3 OUT4EN 4 04 Audio Interface BCP 5 ...
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WM8978 REGISTER B8 ADDR NAME B[15:9] DEC HEX ctrl UPDATE 46 2E Right INP PGA INPGA gain ctrl UPDATE 47 2F Left ADC Boost ctrl PGABOOSTL 48 30 Right ADC Boost PGABOOSTR ctrl 49 31 Output ctrl ...
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Production Data REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as “Reserved” should not be changed from the default. REGISTER BIT LABEL ADDRESS ...
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WM8978 REGISTER BIT LABEL ADDRESS 2 INPPGAENL 1 ADCENR 0 ADCENL 3 (03h) 8 OUT4EN 7 OUT3EN 6 LOUT2EN 5 ROUT2EN 3 RMIXEN 2 LMIXEN 1 DACENR 0 DACENL 4 (04h) 8 BCP 7 LRP 6 DEFAULT DESCRIPTION ...
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Production Data REGISTER BIT LABEL ADDRESS 4:3 FMT 2 DACLRSWAP 1 ADCLRSWAP 0 MONO 5 (05h) 8:6 5 WL8 4:3 DAC_COMP 2:1 ADC_COMP 0 LOOPBACK 6 (06h) 8 CLKSEL 7:5 MCLKDIV w DEFAULT DESCRIPTION 10 Audio interface Data Format Select: ...
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WM8978 REGISTER BIT LABEL ADDRESS 4:2 BCLKDIV (07h) 8:4 3 SLOWCLKEN 8 (08h) 8:6 5:4 OPCLKDIV 3 GPIO1POL 2:0 GPIO1SEL [2:0] w DEFAULT DESCRIPTION 000 Configures the BCLK output frequency, for use when the ...
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Production Data REGISTER BIT LABEL ADDRESS 9 (09h) 8:7 JD_VMID 6 JD_EN 5:4 JD_SEL 10 (0Ah) 8:7 6 SOFTMUTE 5:4 3 DACOSR128 2 AMUTE 1 DACPOLR 0 DACPOLL 11 (0Bh) 8 DACVU 7:0 DACVOLL 12 (0Ch) 8 DACVU 7:0 DACVOLR ...
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WM8978 REGISTER BIT LABEL ADDRESS 13 (0Dh) 8 7:4 JD_EN1 3:0 JD_EN0 14 (0Eh) 8 HPFEN 7 HPFAPP 6:4 HPFCUT 3 ADCOSR 128 2 1 ADCRPOL 0 ADCLPOL 15 (0Fh) 8 ADCVU 7:0 ADCVOLL 16 (10h) 8 ADCVU 7:0 ADCVOLR ...
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Production Data REGISTER BIT LABEL ADDRESS 18 (12h) 8 EQ3DMODE 7 6:5 EQ1C 4:0 EQ1G 19 (13h) 8 EQ2BW 7 6:5 EQ2C 4:0 EQ2G 20 (14h) 8 EQ3BW 7 6:5 EQ3C 4:0 EQ3G 21 (15h) 8 EQ4BW 7 6:5 EQ4C ...
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WM8978 REGISTER BIT LABEL ADDRESS 4:0 EQ5G 24 (18h) 8 LIMEN 7:4 LIMDCY 3:0 LIMATK 25 (19h) 8:7 6:4 LIMLVL 3:0 LIMBOOST w DEFAULT DESCRIPTION 01100 EQ Band 5 Gain Control. See Table 36 for details. 0 Enable the DAC ...
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Production Data REGISTER BIT LABEL ADDRESS 27 (1Bh) 8 NFU 7 NFEN 6:0 NFA0[13:7] 28 (1Ch) 8 NFU 7 6:0 NFA0[6:0] 29 (1Dh) 8 NFU 7 6:0 NFA1[13:7] 30 (1Eh) 8 NFU 7 6:0 NFA1[6:0] 32 (20h) 8:7 ALCSEL 6 ...
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WM8978 REGISTER BIT LABEL ADDRESS 2:0 ALCMINGAIN 33 (21h) 8 7:4 ALCHLD 3:0 ALCLVL 34 (22h) 8 ALCMODE 7:4 ALCDCY [3:0] 3:0 ALCATK w DEFAULT DESCRIPTION 000 Set minimum gain of PGA 000=-12dB 001=-6dB 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB ...
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Production Data REGISTER BIT LABEL ADDRESS 35 (23h) 8:4 3 NGEN 2:0 NGTH 36 (24h) 8:5 4 PLL PRESCALE 3:0 PLLN[3:0] 37 (25h) 8:6 5:0 PLLK[23:18] 38 (26h) 8:0 PLLK[17:9] 39 (27h) 8:0 PLLK[8:0] 40 (28h) 8:0 41 (29h) 8:4 ...
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WM8978 REGISTER BIT LABEL ADDRESS 3:1 BEEPVOL 0 BEEPEN 44 (2Ch) 8 MBVSEL 7 6 R2_2INPPGA 5 RIN2INPPGA 4 RIP2INPPGA 3 2 L2_2INPPGA 1 LIN2INPPGA 0 LIP2INPPGA 45 (2Dh) 8 INPPGAUPDATE 7 INPPGAZCL 6 INPPGAMUTEL w DEFAULT DESCRIPTION 000 AUXR ...
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Production Data REGISTER BIT LABEL ADDRESS 5:0 INPPGAVOLL 46 (2Eh) 8 INPPGAUPDATE 7 INPPGAZCR 6 INPPGAMUTER 5:0 INPPGAVOLR 47 (2Fh) 8 PGABOOSTL 7 6:4 L2_2BOOSTVOL 3 2:0 AUXL2BOOSTVOL 48 (30h) 8 PGABOOSTR 7 w DEFAULT DESCRIPTION 010000 Left channel input ...
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WM8978 REGISTER BIT LABEL ADDRESS 6:4 R2_2BOOSTVOL 3 2:0 AUXR2BOOSTVOL 49 (31h) 8:7 6 DACL2RMIX 5 DACR2LMIX 4 OUT4BOOST 3 OUT3BOOST 2 SPKBOOST 1 TSDEN 0 VROI 50 (32h) 8:6 AUXLMIXVOL 5 AUXL2LMIX w DEFAULT DESCRIPTION 000 Controls the R2 ...
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Production Data REGISTER BIT LABEL ADDRESS 4:2 BYPLMIXVOL 1 BYPL2L MIX 0 DACL2L MIX 51 (33h) 8:6 AUXRMIXVOL 5 AUXR2RMIX 4:2 BYPRMIXVOL 1 BYPR2RMIX 0 DACR2RMIX 52 (34h) 8 HPVU 7 LOUT1ZC 6 LOUT1MUTE w DEFAULT DESCRIPTION 000 Left bypass ...
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WM8978 REGISTER BIT LABEL ADDRESS 5:0 LOUT1VOL 53 (35h) 8 HPVU 7 ROUT1ZC 6 ROUT1MUTE 5:0 ROUT1VOL 54 (36h) 8 SPKVU 7 LOUT2ZC 6 LOUT2MUTE 5:0 LOUT2VOL 55 (37h) 8 SPKVU 7 ROUT2ZC 6 ROUT2MUTE 5:0 ROUT2VOL 56 (38h) 8:7 ...
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Production Data REGISTER BIT LABEL ADDRESS 3 OUT4_2OUT3 2 BYPL2OUT3 1 LMIX2OUT3 0 LDAC2OUT3 57 (39h) 8:7 6 OUT4MUTE 5 HALFSIG 4 LMIX2OUT4 3 LDAC2OUT4 2 BYPR2OUT4 1 RMIX2OUT4 0 RDAC2OUT4 w DEFAULT DESCRIPTION 0 OUT4 mixer output to OUT3 ...
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WM8978 DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 70 Digital Filter Characteristics TERMINOLOGY ...
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Production Data DAC FILTER RESPONSES 20 0 -20 -40 -60 -80 -100 -120 -140 -160 0 0.5 1 Frequency (fs) Figure 48 DAC Digital Filter Frequency Response (128xOSR -20 -40 -60 -80 -100 -120 -140 -160 0 0.5 ...
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WM8978 HIGHPASS FILTER The WM8978 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter 3.7Hz. frequency -10 -15 -20 ...
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Production Data 5-BAND EQUALISER The WM8978 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 58 to Figure 71 show the frequency responses of each filter with a ...
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WM8978 -10 - Frequency (Hz) Figure 63 EQ Band 3 – Peak Filter Centre Frequencies, EQ3BFigure -10 - ...
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Production Data -10 - Frequency (Hz) Figure 66 EQ Band 4 – Peak Filter Centre Frequencies, EQ3BFigure -10 - ...
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WM8978 Figure 71 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with ±12dB gain. The red traces show the cumulative effect of all bands with ...
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Production Data APPLICATION INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 72 Recommended External Component Diagram w WM8978 PD Rev 4.4 June 2009 115 ...
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WM8978 PACKAGE DIAGRAM FL: 32 PIN QFN PLASTIC PACKAGE EXPOSED GROUND 6 PADDLE BOTTOM VIEW A3 C SIDE VIEW SEATING PLANE Exposed lead Half ...
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... Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...