WM8983GEFL/RV Wolfson Microelectronics, WM8983GEFL/RV Datasheet - Page 85

• Manufacturer Part Number: WM8983GEFL/RV
• Description: Audio CODECs Mbl Multimedia CODEC w/ 1W Speaker Driver
• Manufacturer: Wolfson Microelectronics

Specifications of WM8983GEFL/RV

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C

Production Data
AUDIO SAMPLE RATES
MASTER CLOCK AND PHASE LOCKED LOOP (PLL)
w
Table 57 Sample Rate Control
The PLL can be enabled or disabled by the PLLEN register bit.
Table 58 PLLEN Control Bit
The WM8983 filter characteristics for the ADCs and the DACs are set using the SR register bits;
these bits do not change the rate of the audio interface output clocks in Master mode. The cut-offs
for the digital filters and the ALC attack/decay times stated are determined using these values and
assume a 256fs master clock rate.
If a sample rate is required which is not explicitly supported by the SR register settings, then the
closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack,
decay and hold times will scale appropriately.
The WM8983 has an on-chip phase-locked loop (PLL) circuit that can be used to:
Generate master clocks for the WM8983 audio functions from another external clock, e.g. in
telecoms applications.
Generate and output (on pin CSB/GPIO1) a clock for another part of the system that is derived from
an existing audio master clock.
Figure 49 shows the PLL and internal clocking on the WM8983.
R7
Additional
Control
R1
Power
management 1
REGISTER
ADDRESS
REGISTER
ADDRESS
3:1
BIT
5
BIT
SR
LABEL
PLLEN
LABEL
000
0
DEFAULT
DEFAULT
PLL enable
0 = PLL off
1 = PLL on
Approximate sample rate (configures the
coefficients for the internal digital filters):
000 = 48kHz
001 = 32kHz
010 = 24kHz
011 = 16kHz
100 = 12kHz
101 = 8kHz
110-111 = reserved
DESCRIPTION
DESCRIPTION
PD Rev 4.0 November 2006
WM8983
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