CS8420-DSR Cirrus Logic Inc, CS8420-DSR Datasheet - Page 26
CS8420-DSR
Manufacturer Part Number
CS8420-DSR
Description
Audio DSPs IC Digital Audio Sample Rate Convertr
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS8420-CSZ.pdf
(94 pages)
Specifications of CS8420-DSR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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In or Out
In or Out
TCBL
TCBL
TXP(N)
VLRCK
TXP(N)
VLRCK
TXP(N)
Output
Output
VLRCK= ILRCK if SILRPOL = 1.
VLRCK duty cycle is 50%
VLRCK = ILRCK if SILRPOL = 1.
SDIN
VLRCK is a virtual word clock, which may not exist, and is used to illustrate CUV timing.
In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate.
If the serial audio input port is in slave mode and TCBL is an output, the VLRCK=ILRCK if SILRPOL=0 and
If the serial audio input port is in master mode and TCBL is an input, the VLRCK=ILRCK if SILRPOL=0 and
U
Input
Input
Input
SDIN
VCU
Input
Tth
Tth
Z
Z
Z
*Assume MMTLR = 0
*Assume MMTLR = 1
Data [4]
Tsetup
Data [0]
Data [4]
Figure 20. AES3 Transmitter Timing for C, U and V Pin Input Data
VCU[0]
Data [0]*
Data [1]*
Y
Thold
Data [5]
Data [1]
Data [5]
.
AES3 Transmitter in Stereo Mode
VCU[1]
AES3 Transmitter in Mono Mode
U[0]
Y
X
Y
Data [6]
Data [6]
Data [2]
Data [3]*
Data [2]*
VCU[2]
Y
Data [7]
Data [7]
Data [3]
Tsetup = > 7.5 % AES3 frame time
VCU[3]
Thold = 0
Tsetup = > 15 % AES3 frame time
Thold = 0
Tth > 3 OMCK if TCBL is Input
Tth > 3 OMCK if TCBL is Input
U[2]
X
X
X
Data [8]
Data [8]
Data [4]
Data [5]*
Data [4]*
VCU[4]
CS8420
DS245F4
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