CS8420-CSR Cirrus Logic Inc, CS8420-CSR Datasheet - Page 71
CS8420-CSR
Manufacturer Part Number
CS8420-CSR
Description
Audio DSPs IC Digital Audio Sample Rate Convertr
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS8420-CSZ.pdf
(94 pages)
Specifications of CS8420-CSR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DS245F4
13.6
Hardware Mode 5 Description
Hardware Mode 5 data flow is shown in
the serial audio output port. The PRO, COPY, ORIG, EMPH, and AUDIO channel status bits are output on
pins. The decoded C and U bits are also output, clocked by both edges of OLRCK (Master mode only, see
Figure
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodified
to the serial audio output port.
Start-up options are shown in
and the serial audio port format. The following pages contain the detailed pin descriptions for Hardware
mode 5.
(AES3 Receiver Only)
19).
RXP
RXN
RMCK
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
SDOUT
LO
HI
-
-
-
-
AES3 Rx
&
Decoder
VD+
DFC0
RERR
Figure 28. Hardware Mode 5 - AES3 Receiver Only
Table 14. Hardware Mode 5 Start-Up Options
VD+
NVERR
Table
ORIG
DFC1
LO
LO
HI
HI
-
-
14, and allow choice of the serial audio output port as a master or slave,
CHS
Figure
S/AES
COPY ORIG EMPH
EMPH
LO
LO
HI
HI
-
-
C & U bit Data Buffer
28. Audio data is input via the AES3 receiver, and routed to
VD+
H/S
Serial Output Port is Slave
Serial Output Port is Master
Serial Output Format OF1
Serial Output Format OF2
Serial Output Format OF3
Serial Output Format OF5
PRO AUDIO
Function
Serial
Audio
Output
RCBL
OMCK
C
U
OLRCK
OSCLK
SDOUT
CS8420
71
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