WM8993ECS/RV Wolfson Microelectronics, WM8993ECS/RV Datasheet
WM8993ECS/RV
Available stocks
Related parts for WM8993ECS/RV
WM8993ECS/RV Summary of contents
Page 1
... Free-running mode for class D and charge pump Low noise paths bypass all internal mixers Low power consumption DC offset correction removes pops and clicks Ground loop noise cancellation Pre-Production, September 2009, Rev 3.0 Copyright ©2009 Wolfson Microelectronics plc ...
Page 2
WM8993 DESCRIPTION ....................................................................................................... 1 FEATURES............................................................................................................. 1 APPLICATIONS ..................................................................................................... 1 TABLE OF CONTENTS ......................................................................................... 2 BLOCK DIAGRAM ................................................................................................. 4 PIN CONFIGURATION ........................................................................................... 5 ORDERING INFORMATION .................................................................................. 5 PIN DESCRIPTION ................................................................................................ 6 ABSOLUTE MAXIMUM RATINGS ......................................................................... 8 RECOMMENDED OPERATING CONDITIONS ..................................................... 8 ...
Page 3
Pre-Production DIGITAL FILTER CHARACTERISTICS ............................................................. 211 ADC FILTER RESPONSES ....................................................................................... 212 ADC HIGH PASS FILTER RESPONSES ................................................................... 212 DAC FILTER RESPONSES ....................................................................................... 213 DE-EMPHASIS FILTER RESPONSES ...................................................................... 214 APPLICATIONS INFORMATION ....................................................................... 215 RECOMMENDED EXTERNAL COMPONENTS ......................................................... 215 PCB LAYOUT CONSIDERATIONS ...
Page 4
WM8993 BLOCK DIAGRAM w Pre-Production PP, September 2009, Rev 3.0 4 ...
Page 5
... PIN CONFIGURATION 1 SPK A OUTLP SPK B OUTLN SPK C OUTRP D SPKGND E DBVDD F SCLK G LRCLK ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8993ECS/RV -40°C to +85°C Note: Reel quantity = 3500 LINE LINE LINE OUT2P OUT2N OUTFB SPK LINE LINE OUTRN OUT1P OUT1N SPKVDD IN1RN IN1RP ...
Page 6
WM8993 PIN DESCRIPTION PIN NO NAME A5 MICBIAS1 Analogue Output Analogue Output B5 MICBIAS2 C5 IN1LN Analogue Input D5 IN1LP Analogue Input B6 IN2LN/GI7 Analogue Input / Digital Input B7 IN2LP/VRXN Analogue Input C3 IN1RN Analogue Input C4 IN1RP Analogue ...
Page 7
Pre-Production PIN NO NAME B4 LINEOUT1N Analogue Output B3 LINEOUT1P Analogue Output A3 LINEOUT2N Analogue Output A2 LINEOUT2P Analogue Output Analogue Input A4 LINEOUTFB C6 VMIDC Analogue Output D3 GPIO1 Digital Input / Output w TYPE Negative mono line output ...
Page 8
WM8993 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
Page 9
Pre-Production THERMAL PERFORMANCE Thermal analysis should be performed in the intended application to prevent the WM8993 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably the physical properties of the mechanical enclosure, location of the device ...
Page 10
WM8993 ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless ...
Page 11
Pre-Production Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 12
WM8993 Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 13
Pre-Production Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 14
WM8993 Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 15
Pre-Production Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 16
WM8993 Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 17
Pre-Production Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 18
WM8993 Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 19
Pre-Production Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 20
WM8993 Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 21
Pre-Production Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 22
WM8993 Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 23
Pre-Production Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 24
WM8993 Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 25
Pre-Production Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, 1kHz signal 48kHz, PGA gain = 0dB, 24-bit audio data unless otherwise stated. ...
Page 26
WM8993 TYPICAL PERFORMANCE POWER CONSUMPTION Mode Other settings Battery Leakage All supplies except SPKVDD disabled Standby / Sleep Leakage OFF (hermal sensor disabled) No clocks OFF (therm al sensor enabled) No clocks Default state at power-up OFF (therm al sensor ...
Page 27
Pre-Production AUDIO SIGNAL PATHS DIAGRAM w WM8993 PP, September 2009, Rev 3.0 27 ...
Page 28
WM8993 SIGNAL TIMING REQUIREMENTS MASTER CLOCK Figure 2 Master Clock Timing Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V + PARAMETER SYMBOL Master Clock ...
Page 29
Pre-Production AUDIO INTERFACE TIMING MASTER MODE Figure 3 Audio Interface Timing - Master Mode Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, Master Mode, ...
Page 30
WM8993 SLAVE MODE Figure 4 Audio Interface Timing – Slave Mode Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V +25 C, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit ...
Page 31
Pre-Production TDM MODE In TDM mode important that two ADC devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8993 ADCDAT tri-stating at the start and end of the data transmission is described ...
Page 32
WM8993 CONTROL INTERFACE TIMING START SCLK (input SDAT Figure 6 Control Interface Timing Test Conditions DCVDD = 1.2V, AVDD2 = DBVDD = CPVDD = 1.8V, AVDD1 = 3.0V, SPKVDD = 5V, DGND=AGND=CPGND=SPKGND=0V =+25 C, ...
Page 33
Pre-Production DEVICE DESCRIPTION INTRODUCTION The WM8993 is a low power, high quality audio codec designed to interface with a wide range of processors and analogue components. A high level of mixed-signal integration in a very small 3.64 x 3.54mm footprint ...
Page 34
WM8993 The WM8993 uses a standard 2-wire control interface, providing full software control of all features, together with device register readback. An integrated Control Write Sequencer enables automatic scheduling of control sequences; commonly-used signal configurations may be selected using ready- ...
Page 35
Pre-Production INPUT SIGNAL PATH The WM8993 has eight highly flexible analogue input channels, configurable in a large number of combinations four fully differential or single-ended microphone inputs eight mono line inputs or 4 stereo ...
Page 36
WM8993 MICROPHONE INPUTS Up to four microphones can be connected to the WM8993, either in single-ended or differential mode. A dedicated PGA is provided for each microphone input. Two low noise microphone bias circuits are provided, reducing the need for ...
Page 37
Pre-Production MICROPHONE BIAS CONTROL There are two MICBIAS generators which provide low noise reference voltages suitable for biasing electret condenser (ECM) type microphones via an external resistor. Refer to the Applications Information section for recommended external components. The MICBIAS voltages ...
Page 38
WM8993 LINE AND VOICE CODEC INPUTS All eight analogue input pins may be used as line inputs. Each line input has different signal path options, providing flexibility, high performance and low power consumption for many different usage modes. IN1LN and ...
Page 39
Pre-Production INPUT PGA ENABLE The Input PGAs are enabled using register bits IN1L_ENA, IN2L_ENA, IN1R_ENA and IN2R_ENA, as described in Table 2. The Input PGAs must be enabled for microphone input on the respective input pins, or for line input ...
Page 40
WM8993 INPUT PGA CONFIGURATION Each of the Input PGAs can operate in a single-ended or differential mode. In differential mode, both inputs to the PGA are connected to the input source. In single-ended mode, the non-inverting input to the PGA ...
Page 41
Pre-Production INPUT PGA VOLUME CONTROL Each of the four Input PGAs has an independently controlled gain range of -16.5dB to +30dB in 1.5dB steps. The gains on the inverting and non-inverting inputs to the PGAs are always equal. Each Input ...
Page 42
WM8993 REGISTER ADDRESS R27 (1Bh) Right Line Input 3&4 Volume Table 4 Input PGA Volume Control IN1L_VOL[4:0], IN2L_VOL[4:0], IN1R_VOL[4:0], IN2R_VOL[4:0] Table 5 Input PGA Volume Range w BIT LABEL DEFAULT 8 IN2_VU N/A 7 IN2R_MUTE 1b 6 IN2R _ZC 0b ...
Page 43
Pre-Production INPUT MIXER ENABLE The WM8993 has two analogue input mixers which allow the Input PGAs and Line Inputs to be combined in a number of ways and output to the ADCs, Output Mixers, or directly to the output drivers ...
Page 44
WM8993 REGISTER ADDRESS R41 (29h) Input Mixer3 R43 (2Bh) Input Mixer5 Table 7 Left Input Mixer (MIXINL) Volume Control w BIT LABEL DEFAULT 8 IN2L_TO_MIXINL 0b 7 IN2L_MIXINL_VOL 0b 5 IN1L_TO_MIXINL 0b 4 IN1L_MIXINL_VOL 0b 2:0 MIXOUTL_MIXINL_VOL 000b [2:0] (Mute) ...
Page 45
Pre-Production REGISTER ADDRESS R42 (2A) Input Mixer4 R44 (2Ch) Input Mixer6 Table 8 Right Input Mixer (MIXINR) Volume Control w BIT LABEL DEFAULT 8 IN2R_TO_MIXINR 0b 7 IN2R_MIXINR_VOL 0b 5 IN1R_TO_MIXINR 0b 4 IN1R_MIXINR_VOL 0b 2:0 MIXOUTR_MIXINR_VOL 000b [2:0] (Mute) ...
Page 46
WM8993 ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8993 uses stereo 24-bit, 128x oversampled sigma-delta ADCs. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. An oversample rate of 64x can also ...
Page 47
Pre-Production ADCL_VOL or ADCR_VOL Volume (dB) 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 Fh -66.375 10h -66.000 ...
Page 48
WM8993 HIGH PASS FILTER A digital high pass filter is applied by default to the ADC path to remove DC offsets. This filter can also be programmed to remove low frequency noise in voice applications (e.g. wind noise or mechanical ...
Page 49
Pre-Production DIGITAL MIXING The ADC and DAC data can be combined in various ways to support a range of different usage modes. Data from either of the two ADCs can be routed to either the left or the right channel ...
Page 50
WM8993 The polarity of each ADC output signal can be changed under software control using the ADCL_DATINV and ADCR_DATINV register bits. The AIFADCL_SRC and AIFADCR_SRC register bits may be used to select which ADC is used for the left and ...
Page 51
Pre-Production DAC INTERFACE VOLUME BOOST A digital gain function is available at the audio interface to boost the DAC volume when a small signal is received on DACDAT. This is controlled using register bits DAC_BOOST[1:0]. To prevent clipping at the ...
Page 52
WM8993 ADCL_DAC_SVOL or ADCR_DAC_SVOL Table 18 Digital Sidetone Volume w SIDETONE VOLUME (dB) 0000 -36 0001 -33 0010 -30 0011 -27 0100 -24 0101 -21 0110 -18 0111 -15 1000 -12 1001 -9 1010 -6 1011 -3 1100 0 1101 ...
Page 53
Pre-Production DYNAMIC RANGE CONTROL (DRC) The dynamic range controller (DRC circuit which can be enabled in the digital data path of either the ADCs or the DACs. The function of the DRC is to adjust the signal gain ...
Page 54
WM8993 The “knee” in Figure 15 is represented by T and Y, which are determined by register fields DRC_THRESH_COMP and DRC_AMP_COMP respectively. Parameter Y0, the output level for a 0dB input, is not specified directly, but can be calculated from ...
Page 55
Pre-Production REGISTER ADDRESS R123 (7Bh) DRC Control 1 Table 21 DRC Gain Limits DYNAMIC CHARACTERISTICS The dynamic behaviour determines how quickly the DRC responds to changing signal levels. Note that the DRC responds to the average (RMS) signal amplitude over ...
Page 56
WM8993 ANTI-CLIP CONTROL The DRC includes an Anti-Clip feature to avoid signal clipping when the input amplitude rises very quickly. This feature uses a feed-forward technique for early detection of a rising signal level. Signal clipping is avoided by dynamically ...
Page 57
Pre-Production REGISTER ADDRESS R123 (7Bh) DRC Control 1 R125 (7Dh) DRC Control 3 Table 24 DRC Quick-Release Control GAIN SMOOTHING The DRC includes a gain smoothing filter in order to prevent gain ripples. A programmable level of hysteresis is also ...
Page 58
WM8993 INITIALISATION When the DRC is initialised, the gain is set to the level determined by the DRC_STARTUP_GAIN register field. The default setting is 0dB, but values from -3dB to +6dB are available, as described in Table 26. REGISTER ADDRESS ...
Page 59
Pre-Production TM RETUNE MOBILE PARAMETRIC EQUALIZER (EQ) The ReTune of the adjust the frequency characteristic of the output in order to compensate for unwanted frequency characteristics in the loudspeaker (or other output transducer). It can also be ...
Page 60
WM8993 Table 30 EQ Gain Control RETUNE ReTune frequencies and filter bandwidth for each EQ band, in addition to the gain controls already described. This enables the accurately customised for a specific transducer characteristic or desired sound ...
Page 61
Pre-Production EQ FILTER CHARACTERISTICS The filter characteristics for each frequency band are shown in Figure 16 to Figure 20. These figures show the frequency response for all available gain settings, using default cut-off/centre frequencies and bandwidth ...
Page 62
WM8993 DIGITAL TO ANALOGUE CONVERTER (DAC) The WM8993 DACs receive digital input data from the DACDAT pin and via the digital sidetone path. The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation ...
Page 63
Pre-Production DACL_VOL or DACR_VOL Volume (dB) 0h MUTE 1h -71.625 2h -71.250 3h -70.875 4h -70.500 5h -70.125 6h -69.750 7h -69.375 8h -69.000 9h -68.625 Ah -68.250 Bh -67.875 Ch -67.500 Dh -67.125 Eh -66.750 Fh -66.375 10h -66.000 ...
Page 64
WM8993 DAC SOFT MUTE AND SOFT UN-MUTE The WM8993 has a soft mute function which, when enabled, gradually attenuates the volume of the DAC output. When soft mute is disabled, the gain will either gradually ramp back up to the ...
Page 65
Pre-Production The volume ramp rate during soft mute and un-mute is controlled by the DAC_MUTERATE bit. Ramp rates of fs/32 and fs/2 are selectable as shown in Table 34. The ramp rate determines the rate at which the volume will ...
Page 66
WM8993 DAC DE-EMPHASIS Digital de-emphasis can be applied to the DAC playback data; this is appropriate when the data source where pre-emphasis is used in the recording. De-emphasis filtering is available for sample rates of 48kHz, 44.1kHz ...
Page 67
Pre-Production OUTPUT SIGNAL PATH The WM8993 output routing and mixers provide a high degree of flexibility, allowing operation of many simultaneous signal paths through the device to a variety of analogue outputs. The outputs include a ground referenced headphone driver, ...
Page 68
WM8993 OUTPUT SIGNAL PATHS ENABLE The output mixers and drivers can be independently enabled and disabled as described in Table 38. Note that the headphone outputs HPOUT1L and HPOUT1R have dedicated output PGAs and volume controls result, a ...
Page 69
Pre-Production REGISTER ADDRESS R56 (38h) AntiPOP1 Table 38 Output Signal Paths Enable OUTPUT MIXER CONTROL The Output Mixer path select and volume controls are described in Table 39 for the Left Channel (MIXOUTL) and Table 40 for the Right Channel ...
Page 70
WM8993 REGISTER ADDRESS R45 (2Dh) Output Mixer1 R47 (2Fh) Output Mixer3 R45 (2Dh) Output Mixer1 R47 (2Fh) Output Mixer3 R45 (2Dh) Output Mixer1 R49 (31h) Output Mixer5 R45 (2Dh) Output Mixer1 R49 (31h) Output Mixer5 R45 (2Dh) Output Mixer1 R49 ...
Page 71
Pre-Production REGISTER ADDRESS R46 (2Eh) Output Mixer2 R50 (32h) Output Mixer6 R46 (2Eh) Output Mixer2 R48 (30h) Output Mixer4 R46 (2Eh) Output Mixer2 R48 (30h) Output Mixer4 R46 (2Eh) Output Mixer2 R48 (30h) Output Mixer4 R46 (2Eh) Output Mixer2 R48 ...
Page 72
WM8993 VOLUME SETTING Table 41 MIXOUTL and MIXOUTR Volume Range SPEAKER MIXER CONTROL The Speaker Mixer path select and volume controls are described in Table 42 for the Left Channel (SPKMIXL) and Table 43 for the Right Channel (SPKMIXR). Care ...
Page 73
Pre-Production REGISTER ADDRESS Table 42 Left Speaker Mixer (SPKMIXL) Control REGISTER ADDRESS R54 (36h) Speaker Mixer R35 (22h) SPKMIXR Attenuation Table 43 Right Speaker Mixer (SPKMIXR) Control w BIT LABEL DEFAULT SPKMIXL_VOL [1:0] 1:0 11b BIT LABEL DEFAULT MIXINR_TO_SPKMIXR 6 ...
Page 74
WM8993 OUTPUT SIGNAL PATH VOLUME CONTROL There are six output PGAs - MIXOUTLVOL, MIXOUTRVOL, HPOUT1LVOL, HPOUT1RVOL, SPKLVOL and SPKRVOL. Each can be independently controlled, with MIXOUTLVOL and MIXOUTRVOL providing volume control to both the earpiece and line drivers, HPOUT1LVOL and ...
Page 75
Pre-Production The headphone output PGA is configurable between two input sources. The default input to each headphone output PGA is the respective output mixer (MIXOUTL or MIXOUTR). A direct path from the DACL or DACR can be selected using the ...
Page 76
WM8993 The speaker output PGA controls are shown in Table 46.The SPKOUT_VU bits control the loading of the speaker PGA volume data. When SPKOUT_VU is set to 0, the volume control data will be loaded into the respective control register, ...
Page 77
Pre-Production PGA GAIN SETTING Table 47 Output PGA Volume Range w VOLUME (dB) PGA GAIN SETTING 0h -57 1h -56 2h -55 3h -54 4h -53 5h -52 6h -51 7h -50 8h -49 9h -48 Ah -47 Bh -46 ...
Page 78
WM8993 SPEAKER BOOST MIXER Each class D/AB speaker driver has its own boost mixer which performs a dual role. It allows the output from the left speaker mixer (via SPKLVOL), right speaker mixer (via SPKRVOL), or the ‘Direct Voice’ path ...
Page 79
Pre-Production EARPIECE DRIVER MIXER The earpiece driver has a dedicated mixer, HPOUT2MIX, which is controlled using the registers defined in Table 49. The earpiece driver is configurable to select output from the left output mixer (via MIXOUTLVOL), the right output ...
Page 80
WM8993 LINE OUTPUT MIXERS The WM8993 provides two pairs of line outputs, both with highly configurable output mixers. The outputs LINEOUT1N and LINEOUT1P can be configured as two single-ended outputs differential output. In the same manner, LINEOUT2N ...
Page 81
Pre-Production REGISTER ADDRESS Table 50 LINEOUT1N and LINEOUT1P Control LINEOUT2 single-ended mode is selected by setting LINEOUT2_MODE = 1. In single-ended mode, any of three possible signal paths may be enabled: LINEOUT2 differential mode is selected by ...
Page 82
WM8993 REGISTER ADDRESS R30 (1Eh) Line Outputs Volume R53 (35h) Line Mixer2 Table 51 LINEOUT2N and LINEOUT2P Control w BIT LABEL DEFAULT 2 LINEOUT2N_MUTE 1b LINEOUT2P_MUTE LINEOUT2_VOL 0b MIXOUTR_TO_LINEO 6 0b UT2N 5 MIXOUTL_TO_LINEO 0b UT2N 4 ...
Page 83
Pre-Production ANALOGUE OUTPUTS The speaker, headphone, earpiece and line outputs are highly configurable and may be used in many different ways. SPEAKER OUTPUT CONFIGURATIONS The speaker outputs SPKOUTL and SPKOUTR can be driven by either of the speaker mixers, SPKMIXL ...
Page 84
WM8993 Figure 23 Speaker Output Configuration and AC Boost Operation REGISTER ADDRESS R35 (23h) SPKMIXR Attenuation R37 (25h) SPKOUT Boost R54 (36h) Speaker Mixer Table 53 Speaker Mode and Boost Control w BIT LABEL DEFAULT 8 SPKOUT_CLASSAB 0b _MODE 5:3 ...
Page 85
Pre-Production HEADPHONE OUTPUT CONFIGURATIONS The headphone outputs HPOUT1L andHPOUT1R are driven by the headphone output PGAs HPOUT1LVOL and HPOUT1RVOL. Each PGA has its own dedicated volume control, as described in the “Output Signal Path” section. The input to these PGAs ...
Page 86
WM8993 EARPIECE DRIVER OUTPUT CONFIGURATIONS The earpiece driver outputs HPOUT2P and HPOUT2N are driven by the HPOUT2MIX output mixer, which can take inputs from the mixer output PGAs MIXOUTLVOL and MIXOUTRVOL, or from the low power, differential Direct Voice path ...
Page 87
Pre-Production LINEOUT1N_MUTE=0, LINEOUT1P_MUTE=0 LINEOUT2N_MUTE=0, LINEOUT2P_MUTE=0 LINEOUT1_MODE=0 LINEOUT2_MODE=0 IN1L_TO_LINEOUT1P=1 IN1R_TO_LINEOUT2P=1 Figure 25 Differential Line Out from input PGA IN1L (to LINEOUT1) and IN1R (to LINEOUT2) LINEOUT1N_MUTE=0, LINEOUT1P_MUTE=0 LINEOUT2N_MUTE=0, LINEOUT2P_MUTE=0 LINEOUT1_MODE=0 LINEOUT2_MODE=0 MIXOUTL_TO_LINEOUT1P=1 MIXOUTR_TO_LINEOUT2P=1 Figure 27 MIXOUTL and MIXOUTR w Stereo Differential ...
Page 88
WM8993 IN1L IN1R Min = -57dB Max = +6dB Step = 1dB MIXOUTLVOL Min = -57dB Max = +6dB Step = 1dB MIXOUTRVOL IN1L IN1R LINEOUT1N_MUTE=0, LINEOUT1P_MUTE=0 LINEOUT2N_MUTE=0, LINEOUT2P_MUTE=0 LINEOUT1_MODE=1 MIXOUTL_TO_LINEOUT2N=1 MIXOUTR_TO_LINEOUT2P=1 LINEOUT_VMID_BUF_ENA=1 Figure 29 Stereo Single-Ended Line Out from ...
Page 89
Pre-Production GENERAL PURPOSE INPUT/OUTPUT The WM8993 provides a number of GPIO functions to enable interfacing and detection of external hardware and to provide logic outputs to other devices. The input functions can be polled directly or can be used to ...
Page 90
WM8993 REGISTER ADDRESS R20 (14h) IRQ_DEBOU NCE R22 (16h) GPIOCTRL2 R23 (17h) GPIO_POL Table 56 GPIO1 Configuration and Interrupt Control BUTTON DETECT The analogue input pins IN2LN and IN2RN support alternate functions as general purpose digital inputs GPI7 and GPI8 ...
Page 91
Pre-Production REGISTER ADDRESS R22 (16h) GPIOCTRL2 R23 (17h) GPIO_POL Table 57 Button Detect Interrupt Control ACCESSORY DETECTION Current detection is provided on each of the microphone bias sources MICBIAS1 and MICBIAS2. These can be configured to detect when an external ...
Page 92
WM8993 REGISTER ADDRESS R18 (12h) GPIO CTRL 1 R20 (14h) IRQ_DEBOU NCE R22 (16h) GPIOCTRL2 w BIT LABEL DEFAULT 5:4 JD_THR 00 Jack Detect (MICBIAS) Current Detect [1:0] threshold 00 = 150uA 01 = 300uA 10 = 600uA 11 = ...
Page 93
Pre-Production REGISTER ADDRESS R23 (17h) GPIO_POL Table 58 MICBIAS Enable and Interrupt Control When GPIO1_SEL = 1000, 1001, 1010 or 1011, the selected Jack Detect status indication is output on the GPIO1 pin. A logic 1 indicates that the associated ...
Page 94
WM8993 FLL LOCK STATUS OUTPUT The WM8993 maintains a flag indicating the lock status of the FLL, which may be used to control other events if required. The FLL Lock status may be output directly on the GPIO1 pin, and ...
Page 95
Pre-Production The temperature sensor must be enabled by setting the TSHUT_ENA register bit. When the TSHUT_OPDIS is also set, then a device over-temperature condition will cause the speaker outputs (SPKOUTL and SPKOUTR) of the WM8993 to be disabled. REGISTER ADDRESS ...
Page 96
WM8993 CONTROL WRITE SEQUENCER STATUS The WM8993 Control Write Sequencer (WSEQ) can be used to execute a sequence of register write operations in response to a simple trigger event. When the Control Write Sequencer is executing a sequence, normal access ...
Page 97
Pre-Production INTERRUPTS The interrupt status flag IRQ is asserted when any un-masked interrupt input is asserted. It represents the OR’d combination of all the un-masked interrupt inputs. If required, this flag may be inverted using the IRQ_POL register bit. The ...
Page 98
WM8993 The de-bounce function on the GPIO functions enable transient behaviour to be filtered as illustrated below: Figure 32 GPIO De-bounce GPIO SUMMARY Details of the GPIO implementation are shown below. When the GPIO pad is configured as an output, ...
Page 99
Pre-Production The overall GPIO and Interrupt function is illustrated in Figure 35. Figure 35 GPIO Summary w WM8993 PP, September 2009, Rev 3.0 99 ...
Page 100
WM8993 DIGITAL AUDIO INTERFACE The digital audio interface is used for inputting DAC data to the WM8993 and outputting ADC data from it. The digital audio interface uses four pins: • • • • The clock signals BCLK and LRCLK ...
Page 101
Pre-Production OPERATION WITH TDM Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same bus. The WM8993 ADCs and DACs support TDM in master and slave modes for all data formats and word lengths. TDM is ...
Page 102
WM8993 BCLK FREQUENCY The BCLK frequency is controlled relative to CLK_SYS by the BCLK_DIV divider. Internal clock divide and phase control mechanisms ensure that the BCLK and LRCLK edges will occur in a predictable and repeatable position relative to each ...
Page 103
Pre-Production Figure 43 I2S Justified Audio Interface (assuming n-bit word length) In DSP mode, the left channel MSB is available on either the 1 edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data immediately ...
Page 104
WM8993 Figure 46 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave) Figure 47 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave) PCM operation is supported in DSP interface mode. WM8993 ADC data that is output on the Left Channel will ...
Page 105
Pre-Production Figure 48 TDM in Right-Justified Mode Figure 49 TDM in Left-Justified Mode Figure 50 TDM in I Figure 51 TDM in DSP Mode Mode WM8993 PP, September 2009, Rev 3.0 105 ...
Page 106
WM8993 Figure 52 TDM in DSP Mode B DIGITAL AUDIO INTERFACE CONTROL The register bits controlling audio data format, word length, left/right channel data source and TDM are summarised in Table 65. REGISTER ADDRESS R4 (04h) Audio Interface (1) w ...
Page 107
Pre-Production REGISTER ADDRESS R5 (05h) Audio Interface (2) Table 65 Digital Audio Interface Data Control AUDIO INTERFACE OUTPUT TRI-STATE Register bit AIF_TRIS can be used to tri-state the audio interface pins as described in Table 66. All digital audio interface ...
Page 108
WM8993 Figure 53 Digital Audio Interface Clock Control REGISTER ADDRESS R4 (04h) Audio Interface (1) R6 (06h) Clocking (1) R8 (08h) Audio Interface (3) R9 (09h) Audio Interface (4) Table 67 Digital Audio Interface Clock Control w BIT LABEL DEFAULT ...
Page 109
Pre-Production COMPANDING The WM8993 supports A-law and μ-law companding on both transmit (ADC) and receive (DAC) sides as shown in Table 68. REGISTER ADDRESS R5 (05h) Audio Interface (2) Table 68 Companding Control Companding involves using a piecewise linear approximation ...
Page 110
WM8993 Figure 54 μ-Law Companding 120 100 Figure 55 A-Law Companding w u-law Companding 120 100 0.1 0.2 0.3 0.4 Normalised Input A-law Companding 0.2 0.4 Normalised Input ...
Page 111
Pre-Production LOOPBACK Setting the LOOPBACK register bit enables digital loopback. When this bit is set, the ADC digital data output is routed to the DAC digital data input path. The digital audio interface input (DACDAT) is not used when LOOPBACK ...
Page 112
WM8993 CLOCKING AND SAMPLE RATES The internal clocks for the WM8993 are all derived from a common internal clock source, CLK_SYS. This clock is the reference for the ADCs, DACs, DSP core functions, digital audio interface, Class D switching amplifier, ...
Page 113
Pre-Production MCLK_INV MCLK_SRC GPIO1 MCLK BCLK LRCLK SR_MODE SAMPLE_RATE [2:0] CLK_SYS_RATE [3:0] DAC_OSR128 MCLK_SRC selects master clock source (MCLK pin or GPIO1 pin). FLL_CLK_SRC selects the input reference for FLL oscillator. Internal clocks are derived from CLK_SYS. These are enabled ...
Page 114
WM8993 CLK_SYS CONTROL The MCLK_SRC bit is used to select the MCLK source. The source may be either MCLK or GPIO1. The selected source may also be inverted by setting the register bit MCLK_INV. Note that it is not recommended ...
Page 115
Pre-Production AUTOMATIC CLOCKING CONFIGURATION The WM8993 supports a wide range of standard audio sample rates from 8kHz to 48kHz. The Automatic Clocking Configuration mode simplifies the configuration of the clock dividers in the WM8993 by deriving most of the necessary ...
Page 116
WM8993 ADC / DAC CLOCK CONTROL The clocking of the ADC and DAC circuits is derived from CLK_DSP. This signal is generated from CLK_SYS and is separately enabled, using the register bit CLK_SYS_ENA. The ADC and DAC sample rates are ...
Page 117
Pre-Production REGISTER ADDRESS R14 (0Eh) ADC CTRL R65 (41h) Clocking 3 R66 (42h) Clocking 4 Table 74 ADC / DAC Clock Control 256K, DC SERVO, CLASS D CLOCK CONTROL Clocking is required to support a variety of other functions on ...
Page 118
WM8993 REGISTER ADDRESS R6 (06h) Clocking 1 R65 (41h) Clocking 3 R66 (42h) Clocking 4 Table 75 256k, DC Servo, Class D Clock Control w BIT LABEL DEFAULT 8:6 DCLK_DIV 111 [2:0] 13:10 CLK_DCS_DIV 1000 [3:0] 6:1 CLK_256K_DIV 2Fh [5:0] ...
Page 119
Pre-Production OPCLK CONTROL A clock output (OPCLK) derived from CLK_SYS may be output on the GPIO1 pin. This clock is enabled by register bit OPCLK_ENA, and its frequency is controlled by OPCLK_DIV. This output of this clock is also dependent ...
Page 120
WM8993 TOCLK_RATE Table 78 TOCLK Rates BCLK AND LRCLK CONTROL In master mode, BCLK is derived from CLK_SYS via a programmable division set by BCLK_DIV. In master mode, LRCLK is derived from BCLK via a programmable division set by LRCLK_RATE. ...
Page 121
Pre-Production The FLL output frequency is generated according to the following equation: The FLL operating frequency the input frequency, as determined by FLL_CLK_REF_DIV. REF F must be in the range 90-100 MHz. Frequencies outside this range cannot ...
Page 122
WM8993 REGISTER ADDRESS R60 (3Ch) FLL Control 1 R61 (3Dh) FLL Control 2 R62 (3Eh) FLL Control 3 R63 (3Fh) FLL Control 4 w BIT LABEL DEFAULT 2 FLL_FRAC 0 1 FLL_OSC_ENA 0 0 FLL_ENA 0 10:8 FLL_OUTDIV 000 [2:0] ...
Page 123
Pre-Production REGISTER ADDRESS R64 (40h) FLL Control 5 Table 81 FLL Register Map FREE-RUNNING FLL CLOCK The FLL can generate a clock signal even when no external reference is available. However, it should be noted that the accuracy of this ...
Page 124
WM8993 REGISTER ADDRESS R64 (40h) FLL Control 5 Table 82 FLL Free-Running Mode In both cases described above, the FLL must be selected as the CLK_SYS source by setting SYSCLK_SRC (see Table 72). The free-running FLL modes are not sufficiently ...
Page 125
Pre-Production EXAMPLE FLL SETTINGS Table 83 provides example FLL settings for generating common CLK_SYS frequencies from a variety of low and high frequency reference inputs FLL_CLK_ REF OUT REF_DIV 32.000 12.288 0h kHz MHz (divide by 1) 32.000 ...
Page 126
WM8993 CONTROL INTERFACE The WM8993 is controlled by writing to registers through a 2-wire serial control interface. Readback is available for all registers, including device ID, power management status and GPIO status. The WM8993 is a slave device on the ...
Page 127
Pre-Production The sequence of signals associated with a single register write operation is illustrated in Figure 57. Figure 57 Control Interface Register Write The sequence of signals associated with a single register read operation is illustrated in Figure 58. Figure ...
Page 128
WM8993 8 bits S Device ID A Register Address RW (0) Figure 59 Single Register Write to Specified Address Figure 60 Single Register Read from Specified Address Figure 61 Multiple Register Write to Specified Address using Auto-increment Figure 62 Multiple ...
Page 129
Pre-Production CONTROL WRITE SEQUENCER The Control Write Sequencer is a programmable unit that forms part of the WM8993 control interface logic. It provides the ability to perform a sequence of register write operations with the minimum of demands on the ...
Page 130
WM8993 REGISTER ADDRESS R70 (46h) Write Sequencer 0 R73 (49h) Write Sequencer 3 R74 (4Ah) Write Sequencer 4 R75 (4Bh) Write Sequencer 5 Table 85 Write Sequencer Control - Initiating a Sequence PROGRAMMING A SEQUENCE A sequence consists of write ...
Page 131
Pre-Production WSEQ_DATA_WIDTH is a 3-bit field which identifies the width of the data block to be written. This enables selected portions of a Control Register to be updated without any concern for other bits within the same register, eliminating the ...
Page 132
WM8993 Note that a ‘Dummy’ write can be inserted into a control sequence by commanding the sequencer to write a value bit 0 of Register R255 (FFh). This is effectively a write to a non-existent register location. ...
Page 133
Pre-Production The following default control sequences are provided: 1. Headphone Cold Start-Up - This sequence powers up the headphone driver and charge pump. It commands the DC Servo to perform offset correction. It enables the master bias required for analogue ...
Page 134
WM8993 WSEQ REGISTER WIDTH INDEX ADDRESS 0 (00h) R57 (39h) 5 bits 1 (01h) R1 (01h) 3 bits 2 (02h) R76 (4Ch) 1 bits 3 (03h) R1 (01h) 3 bits 4 (04h) R96 (60h) 5 bits 5 (05h) R84 (54h) ...
Page 135
Pre-Production Headphone Warm Start-Up The Headphone Warm Start-Up sequence can be initiated by writing 0108h to Register 73 (49h). This single operation starts the Control Write Sequencer at Index Address 8 (08h) and executes the sequence defined in Table 88. ...
Page 136
WM8993 Speaker Start-Up The Speaker Start-Up sequence can be initiated by writing 0110h to Register 73 (49h). This single operation starts the Control Write Sequencer at Index Address 16 (10h) and executes the sequence defined in Table 89. This sequence ...
Page 137
Pre-Production Line Output Start-Up The Line Output Start-Up sequence can be initiated by writing 0119h to Register 73 (49h). This single operation starts the Control Write Sequencer at Index Address 25 (19h) and executes the sequence defined in Table 91. ...
Page 138
WM8993 Speaker and Headphone Fast Shut-Down The Speaker and Headphone Fast Shut-Down sequence can be initiated by writing 0122h to Register 73 (49h). This single operation starts the Control Write Sequencer at Index Address 34 (22h) and executes the sequence ...
Page 139
Pre-Production Generic Shut-Down The Generic Shut-Down sequence can be initiated by writing 012Ah to Register 73 (49h). This single operation starts the Control Write Sequencer at Index Address 42 (2Ah) and executes the sequence defined in Table 93. This sequence ...
Page 140
WM8993 WSEQ REGISTER WIDTH INDEX ADDRESS 56 R56 (38h) 1 bit (38h) 57 R55 (37h) 1 bit (39h) 58 R57 (39h) 6 bits (3Ah) Table 93 Generic Shut-Down Default Sequence POWER SEQUENCES AND POP SUPPRESSION CONTROL The WM8993 incorporates a ...
Page 141
Pre-Production REGISTER ADDRESS R56 (38h) AntiPOP1 Table 95 Line Output Discharge Control VMID REFERENCE DISCHARGE CONTROL The VMID reference can be actively discharged to AGND through internal resistors. This is desirable at start-up in order to achieve a known initial ...
Page 142
WM8993 Step 1 Step 2 Step 3 Step 4 Table 98 Headphone Output Enable Sequence Step 1 Step 2 Table 99 Headphone Output Disable Sequence The sequences described above in Table 98 and Table 99 are implemented automatically by the ...
Page 143
Pre-Production REGISTER ADDRESS Table 100 Pop Suppression Control EXAMPLE CONTROL SEQUENCES The default control sequences (see “Control Write Sequencer”) contain only the register writes necessary to enable or disable specific output drivers therefore necessary to configure the signal ...
Page 144
WM8993 REGISTER R10 (0Ah) R73 (49h) R45 (2Dh) R46 (2Eh) R3 (03h) Table 102 DAC to Headphone Direct Shut-Down Sequence CHARGE PUMP The WM8993 incorporates a dual-mode Charge Pump which generates the supply rails for the headphone output drivers, HPOUT1L ...
Page 145
Pre-Production Note that the charge pump clock is derived from internal clock CLK_SYS; either MCLK or the FLL output selectable using the SYSCLK_SRC bit. Under normal circumstances an external clock signal must be present for the charge pump to function. ...
Page 146
WM8993 DC SERVO The WM8993 provides a DC servo circuit on the headphone outputs HPOUT1L and HPOUT1R in order to remove DC offset from these ground-referenced outputs. When enabled, the DC servo ensures that the DC level of these outputs ...
Page 147
Pre-Production REGISTER ADDRESS R84 (54h) DC Servo 0 R87 (57h) DC Servo 3 R88 (58h) DC Servo Readback 0 w BIT LABEL DEFAULT 5 DCS_TRIG_START 0 UP_1 4 DCS_TRIG_START 0 UP_0 3 DCS_TRIG_DAC_W 0 R_0 2 DCS_TRIG_DAC_W 0 R_0 1 ...
Page 148
WM8993 REGISTER ADDRESS Table 104 DC Servo Enable and Start-Up Modes DC SERVO ACTIVE MODES The DC Servo modes described above are suitable for initialising the DC offset correction circuit on the Headphone outputs as part of a controlled start-up ...
Page 149
Pre-Production REGISTER ADDRESS R84 (54h) DC Servo 0 R85 (55h) DC Servo 1 Table 105 DC Servo Active Modes DC SERVO READBACK The current DC offset value for each Headphone output channel can be read from Registers R89 and R90, ...
Page 150
WM8993 REFERENCE VOLTAGES AND MASTER BIAS This section describes the analogue reference voltage and bias current controls. It also describes the VMID soft-start circuit for pop suppressed start-up and shut-down. Note that, under the recommended usage conditions of the WM8993, ...
Page 151
Pre-Production REGISTER ADDRESS R57 (39h) AntiPOP2 Table 108 Soft Start Control w BIT LABEL DEFAULT VMID_RAMP [1:0] 6:5 10 STARTUP_BIAS_ 2 0 ENA 1 BIAS_SRC 1 WM8993 DESCRIPTION VMID soft start enable / slew rate control 00 = Normal / ...
Page 152
WM8993 POWER MANAGEMENT POWER MANAGEMENT REGISTERS The WM8993 has four control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To minimise pop or click noise important to ...
Page 153
Pre-Production REGISTER ADDRESS R3 (03h) Power Management (3) w BIT LABEL DEFAULT 11 OPCLK_ENA 0b 9 MIXINL_ENA 0b 8 MIXINR_ENA 0b 7 IN2L_ENA 0b 6 IN1L_ENA 0b 5 IN2R_ENA 0b 4 IN1R_ENA 0b 1 ADCL_ENA 0b 0 ADCR_ENA 0b 13 ...
Page 154
WM8993 REGISTER ADDRESS R60 (3Ch) FLL Control 1 R70 (46h) Write Sequencer 0 R76 (4Ch) Charge Pump 1 R84 (54h) DC Servo 0 R98 (62h Table 109 Power Management w BIT LABEL DEFAULT 8 SPKLVOL_ENA 0b 7 MIXOUTLVOL_E ...
Page 155
Pre-Production CHIP RESET AND ID The device ID can be read back from register 0. Writing to this register will reset the device. REGISTER ADDRESS R0 (00h) Software Reset Table 110 Chip Reset and ID POWER ON RESET The WM8993 ...
Page 156
WM8993 Figure 67 Power On Reset timing - DCVDD enabled first The POR ¯ ¯ ¯ signal is undefined until AVDD1 or AVDD2 has exceeded the minimum threshold, V Once this threshold has been exceeded, POR condition, all writes to ...
Page 157
Pre-Production THERMAL SHUTDOWN The WM8993 incorporates a temperature sensor which detects when the device temperature is within normal limits or if the device is approaching a hazardous temperature condition. The Temp OK flag can be polled at any time, or ...
Page 158
WM8993 REGISTER MAP w Pre-Production PP, September 2009, Rev 3.0 158 ...
Page 159
Pre-Production w WM8993 PP, September 2009, Rev 3.0 159 ...
Page 160
WM8993 w Pre-Production PP, September 2009, Rev 3.0 160 ...
Page 161
Pre-Production REGISTER BITS BY ADDRESS REGISTER BIT LABEL ADDRESS R0 (00h) 15:0 SW_RESET[15 Software :0] Reset Register 00h Software Reset REGISTER BIT LABEL ADDRESS R1 (01h) 13 SPKOUTR_EN Power A Managemen t (1) 12 SPKOUTL_EN A 11 HPOUT2_ENA HPOUT1L_EN 9 ...
Page 162
WM8993 REGISTER BIT LABEL ADDRESS R2 (02h) TSHUT_ENA 14 Power Managemen t (2) 13 TSHUT_OPDIS 11 OPCLK_ENA 9 MIXINL_ENA MIXINR_ENA 8 IN2L_ENA 7 6 IN1L_ENA 5 IN2R_ENA 4 IN1R_ENA 1 ADCL_ENA 0 ADCR_ENA Register 02h Power Management (2) w DEFAULT ...
Page 163
Pre-Production REGISTER BIT LABEL ADDRESS R3 (03h) 13 LINEOUT1N_E Power NA Managemen t (3) 12 LINEOUT1P_E NA LINEOUT2N_E 11 NA LINEOUT2P_E SPKRVOL_EN A SPKLVOL_EN MIXOUTLVOL_ ENA MIXOUTRVOL 6 _ENA 5 MIXOUTL_EN A 4 MIXOUTR_EN ...
Page 164
WM8993 REGISTER BIT LABEL ADDRESS R4 (04h) AIFADCL_SRC 15 Audio Interface (1) 14 AIFADCR_SR C 13 AIFADC_TDM 12 AIFADC_TDM_ CHAN 9 BCLK_DIR AIF_BCLK_INV 8 AIF_LRCLK_IN 7 V 6:5 AIF_WL[1:0] 4:3 AIF_FMT[1:0] Register 04h Audio Interface (1) w DEFAULT DESCRIPTION Left ...
Page 165
Pre-Production REGISTER BIT LABEL ADDRESS R5 (05h) 15 AIFDACL_SRC Audio Interface (2) 14 AIFDACR_SR C 13 AIFDAC_TDM 12 AIFDAC_TDM_ CHAN DAC_BOOST[1 11:10 :0] 4 DAC_COMP 3 DAC_COMPM ODE 2 ADC_COMP 1 ADC_COMPM ODE LOOPBACK 0 Register 05h Audio Interface (2) ...
Page 166
WM8993 REGISTER BIT LABEL ADDRESS R6 (06h) TOCLK_RATE 15 Clocking 1 14 TOCLK_ENA 12:9 OPCLK_DIV[3: 0] 8:6 DCLK_DIV[2:0] 4:1 BCLK_DIV[3:0] Register 06h Clocking 1 w DEFAULT DESCRIPTION TOCLK Rate Divider (/ ...
Page 167
Pre-Production REGISTER BIT LABEL ADDRESS R7 (07h) 15 MCLK_SRC Clocking 2 14 SYSCLK_SRC 12 MCLK_DIV 10 MCLK_INV ADC_DIV[2:0] 7:5 4:2 DAC_DIV[2:0] Register 07h Clocking 2 w DEFAULT DESCRIPTION 0 MCLK Source Select 0 = MCLK pin 1 = GPIO1 pin ...
Page 168
WM8993 REGISTER BIT LABEL ADDRESS R8 (08h) AIF_MSTR1 15 Audio Interface (3) Register 08h Audio Interface (3) REGISTER BIT LABEL ADDRESS R9 (09h) 13 AIF_TRIS Audio Interface (4) 11 LRCLK_DIR 10:0 LRCLK_RATE[ 10:0] Register 09h Audio Interface (4) REGISTER BIT ...
Page 169
Pre-Production REGISTER BIT LABEL ADDRESS 5:4 DEEMPH[1:0] 2 DAC_MUTE DACL_DATINV 1 DACR_DATIN 0 V Register 0Ah DAC CTRL REGISTER BIT LABEL ADDRESS R11 (0Bh) 8 DAC_VU Left DAC Digital Volume 7:0 DACL_VOL[7:0 ] Register 0Bh Left DAC Digital Volume REGISTER ...
Page 170
WM8993 REGISTER BIT LABEL ADDRESS R13 (0Dh) ADCL_DAC_S 12:9 Digital Side VOL[3:0] Tone 8:5 ADCR_DAC_S VOL[3:0] 3:2 ADC_TO_DAC L[1:0] 1:0 ADC_TO_DAC R[1:0] Register 0Dh Digital Side Tone REGISTER BIT LABEL ADDRESS R14 (0Eh) 9 ADC_OSR128 ADC CTRL 8 ADC_HPF 6:5 ...
Page 171
Pre-Production REGISTER BIT LABEL ADDRESS R15 (0Fh) 8 ADC_VU Left ADC Digital Volume 7:0 ADCL_VOL[7:0 ] Register 0Fh Left ADC Digital Volume REGISTER BIT LABEL ADDRESS R16 (10h) 8 ADC_VU Right ADC Digital Volume 7:0 ADCR_VOL[7: 0] Register 10h Right ...
Page 172
WM8993 REGISTER BIT LABEL ADDRESS 9 JD1_EINT 8 FLL_LOCK_EI NT 7 GPI8_EINT GPI7_EINT 6 0 GPIO1_EINT Register 12h GPIO CTRL 1 REGISTER BIT LABEL ADDRESS R19 (13h) 5 GPIO1_PU GPIO1 4 GPIO1_PD 3:0 GPIO1_SEL[3: 0] Register 13h GPIO1 w DEFAULT ...
Page 173
Pre-Production REGISTER BIT LABEL ADDRESS R20 (14h) 15 JD2_SC_DB IRQ_DEBO UNCE 14 JD2_DB 13 WSEQ_DB 11 TEMPOK_DB JD1_SC_DB 10 9 JD1_DB 8 FLL_LOCK_DB 7 GPI8_DB 3 GPI7_DB GPIO1_DB 0 Register 14h IRQ_DEBOUNCE REGISTER BIT LABEL ADDRESS R21 (15h) 6 INPUTS_CLAM ...
Page 174
WM8993 REGISTER BIT LABEL ADDRESS R22 (16h) IM_JD2_EINT 13 GPIOCTRL 2 12 IM_JD2_SC_EI NT 11 IM_TEMPOK_ EINT 10 IM_JD1_SC_EI NT 9 IM_JD1_EINT IM_FLL_LOCK 8 _EINT IM_GPI8_EINT 6 5 IM_GPIO1_EIN T 4 GPI8_ENA 2 IM_GPI7_EINT 1 IM_WSEQ_EIN T GPI7_ENA 0 Register ...
Page 175
Pre-Production REGISTER BIT LABEL ADDRESS R23 (17h) 15 JD2_SC_POL GPIO_POL 14 JD2_POL 13 WSEQ_POL IRQ_POL 12 11 TEMPOK_POL 10 JD1_SC_POL 9 JD1_POL 8 FLL_LOCK_PO L 7 GPI8_POL 6 GPI7_POL 0 GPIO1_POL Register 17h GPIO_POL w DEFAULT DESCRIPTION 0 MICBIAS2 Short ...
Page 176
WM8993 REGISTER BIT LABEL ADDRESS R24 (18h) IN1_VU 8 Left Line Input 1&2 Volume 7 IN1L_MUTE IN1L_ZC 6 4:0 IN1L_VOL[4:0] Register 18h Left Line Input 1&2 Volume REGISTER BIT LABEL ADDRESS R25 (19h) 8 IN2_VU Left Line Input 3&4 Volume ...
Page 177
Pre-Production REGISTER BIT LABEL ADDRESS R26 (1Ah) 8 IN1_VU Right Line Input 1&2 Volume IN1R_MUTE 7 6 IN1R_ZC 4:0 IN1R_VOL[4:0] Register 1Ah Right Line Input 1&2 Volume REGISTER BIT LABEL ADDRESS R27 (1Bh) 8 IN2_VU Right Line Input 3&4 Volume ...
Page 178
WM8993 REGISTER BIT LABEL ADDRESS R28 (1Ch) HPOUT1_VU 8 Left Output Volume 7 HPOUT1L_ZC 6 HPOUT1L_MU TE_N 5:0 HPOUT1L_VO L[5:0] Register 1Ch Left Output Volume REGISTER BIT LABEL ADDRESS R29 (1Dh) HPOUT1_VU 8 Right Output Volume 7 HPOUT1R_ZC 6 HPOUT1R_MU ...
Page 179
Pre-Production REGISTER BIT LABEL ADDRESS R30 (1Eh) 6 LINEOUT1N_M Line Outputs UTE Volume 5 LINEOUT1P_M UTE 4 LINEOUT1_VO L LINEOUT2N_M 2 UTE LINEOUT2P_M 1 UTE 0 LINEOUT2_VO L Register 1Eh Line Outputs Volume REGISTER BIT LABEL ADDRESS R31 (1Fh) 5 ...
Page 180
WM8993 REGISTER BIT LABEL ADDRESS R32 (20h) MIXOUT_VU 8 Left OPGA Volume 7 MIXOUTL_ZC 6 MIXOUTL_MU TE_N 5:0 MIXOUTL_VOL [5:0] Register 20h Left OPGA Volume REGISTER BIT LABEL ADDRESS R33 (21h) MIXOUT_VU 8 Right OPGA Volume 7 MIXOUTR_ZC 6 MIXOUTR_MU ...
Page 181
Pre-Production REGISTER BIT LABEL ADDRESS R34 (22h) 5 MIXINL_SPKMI SPKMIXL XL_VOL Attenuation 4 IN1LP_SPKMI XL_VOL 3 MIXOUTL_SPK MIXL_VOL 2 DACL_SPKMIX L_VOL 1:0 SPKMIXL_VOL [1:0] Register 22h SPKMIXL Attenuation REGISTER BIT LABEL ADDRESS R35 (23h) 8 SPKOUT_CLA SPKMIXR SSAB_MODE Attenuation 5 ...
Page 182
WM8993 REGISTER BIT LABEL ADDRESS R36 (24h) VRX_TO_SPK 5 SPKOUT OUTL Mixers 4 SPKMIXL_TO_ SPKOUTL SPKMIXR_TO_ 3 SPKOUTL 2 VRX_TO_SPK OUTR 1 SPKMIXL_TO_ SPKOUTR SPKMIXR_TO_ 0 SPKOUTR Register 24h SPKOUT Mixers REGISTER BIT LABEL ADDRESS R37 (25h) SPKOUTL_BO 5:3 SPKOUT ...
Page 183
Pre-Production REGISTER BIT LABEL ADDRESS R38 (26h) 8 SPKOUT_VU Speaker Volume Left SPKOUTL_ZC 7 6 SPKOUTL_MU TE_N SPKOUTL_VO 5:0 L[5:0] Register 26h Speaker Volume Left REGISTER BIT LABEL ADDRESS R39 (27h) SPKOUT_VU 8 Speaker Volume Right 7 SPKOUTR_ZC 6 SPKOUTR_MU ...
Page 184
WM8993 REGISTER BIT LABEL ADDRESS R40 (28h) IN2LP_TO_IN2 7 Input Mixer2 L 6 IN2LN_TO_IN2 L 5 IN1LP_TO_IN1 L 4 IN1LN_TO_IN1 L 3 IN2RP_TO_IN2 R IN2RN_TO_IN 2 2R IN1RP_TO_IN1 IN1RN_TO_IN 1R Register 28h Input Mixer2 REGISTER BIT LABEL ...
Page 185
Pre-Production REGISTER BIT LABEL ADDRESS R42 (2Ah) 8 IN2R_TO_MIXI Input Mixer4 NR 7 IN2R_MIXINR_ VOL 5 IN1R_TO_MIXI NR 4 IN1R_MIXINR_ VOL MIXOUTR_MIX 2:0 INR_VOL[2:0] Register 2Ah Input Mixer4 REGISTER BIT LABEL ADDRESS R43 (2Bh) 8:6 IN1LP_MIXINL Input Mixer5 _VOL[2:0] 2:0 ...
Page 186
WM8993 REGISTER BIT LABEL ADDRESS R44 (2Ch) IN1RP_MIXINR 8:6 Input Mixer6 _VOL[2:0] 2:0 VRX_MIXINR_ VOL[2:0] Register 2Ch Input Mixer6 REGISTER BIT LABEL ADDRESS R45 (2Dh) 8 DACL_TO_HP Output OUT1L Mixer1 7 MIXINR_TO_M IXOUTL MIXINL_TO_MI 6 XOUTL 5 IN2RN_TO_MI XOUTL 4 ...
Page 187
Pre-Production REGISTER BIT LABEL ADDRESS R46 (2Eh) 8 DACR_TO_HP Output OUT1R Mixer2 7 MIXINL_TO_MI XOUTR 6 MIXINR_TO_M IXOUTR 5 IN2LN_TO_MI XOUTR 4 IN2RN_TO_MI XOUTR 3 IN1L_TO_MIX OUTR IN1R_TO_MIX 2 OUTR 1 IN2RP_TO_MI XOUTR 0 DACR_TO_MI XOUTR Register 2Eh Output Mixer2 ...
Page 188
WM8993 REGISTER BIT LABEL ADDRESS 2:0 IN1L_MIXOUT L_VOL[2:0] Register 2Fh Output Mixer3 REGISTER BIT LABEL ADDRESS R48 (30h) 11:9 IN2RP_MIXOU Output TR_VOL[2:0] Mixer4 8:6 IN2RN_MIXOU TR_VOL[2:0] 5:3 IN1L_MIXOUT R_VOL[2:0] 2:0 IN1R_MIXOUT R_VOL[2:0] Register 30h Output Mixer4 w DEFAULT DESCRIPTION 000 ...
Page 189
Pre-Production REGISTER BIT LABEL ADDRESS R49 (31h) 11:9 DACL_MIXOU Output TL_VOL[2:0] Mixer5 8:6 IN2RN_MIXOU TL_VOL[2:0] 5:3 MIXINR_MIXO UTL_VOL[2:0] 2:0 MIXINL_MIXO UTL_VOL[2:0] Register 31h Output Mixer5 REGISTER BIT LABEL ADDRESS R50 (32h) 11:9 DACR_MIXOU Output TR_VOL[2:0] Mixer6 IN2LN_MIXOU 8:6 TR_VOL[2:0] 5:3 ...
Page 190
WM8993 REGISTER BIT LABEL ADDRESS Register 32h Output Mixer6 REGISTER BIT LABEL ADDRESS R51 (33h) 5 VRX_TO_HPO HPOUT2 UT2 Mixer 4 MIXOUTLVOL_ TO_HPOUT2 3 MIXOUTRVOL _TO_HPOUT2 Register 33h HPOUT2 Mixer REGISTER BIT LABEL ADDRESS R52 (34h) 6 MIXOUTL_TO_ Line Mixer1 ...
Page 191
Pre-Production REGISTER BIT LABEL ADDRESS R53 (35h) 6 MIXOUTR_TO Line Mixer2 _LINEOUT2N MIXOUTL_TO_ 5 LINEOUT2N 4 LINEOUT2_M ODE 2 IN1L_TO_LINE OUT2P 1 IN1R_TO_LINE OUT2P MIXOUTR_TO 0 _LINEOUT2P Register 35h Line Mixer2 REGISTER BIT LABEL ADDRESS R54 (36h) 8 SPKAB_REF_ Speaker ...
Page 192
WM8993 REGISTER BIT LABEL ADDRESS 2 MIXOUTR_TO _SPKMIXR 1 DACL_TO_SP KMIXL 0 DACR_TO_SP KMIXR Register 36h Speaker Mixer REGISTER BIT LABEL ADDRESS R55 (37h) 7 LINEOUT1_FB Additional Control LINEOUT2_FB 6 0 VROI Register 37h Additional Control REGISTER BIT LABEL ADDRESS ...
Page 193
Pre-Production REGISTER BIT LABEL ADDRESS R57 (39h) 6:5 VMID_RAMP[1 AntiPOP2 :0] 3 VMID_BUF_EN A 2 STARTUP_BIA S_ENA BIAS_SRC 1 VMID_DISCH 0 Register 39h AntiPOP2 REGISTER BIT LABEL ADDRESS R58 (3Ah) 7:6 JD_SCTHR[1:0 MICBIAS ] JD_THR[1:0] 5:4 2 JD_ENA MICB2_LVL 1 ...
Page 194
WM8993 REGISTER BIT LABEL ADDRESS R60 (3Ch) FLL_FRAC 2 FLL Control 1 1 FLL_OSC_EN A FLL_ENA 0 Register 3Ch FLL Control 1 REGISTER BIT LABEL ADDRESS R61 (3Dh) FLL_OUTDIV[2 10:8 FLL Control :0] 2 6:4 FLL_CTRL_RA TE[2:0] 2:0 FLL_FRATIO[2 :0] ...
Page 195
Pre-Production REGISTER BIT LABEL ADDRESS R62 (3Eh) 15:0 FLL_K[15:0] FLL Control 3 Register 3Eh FLL Control 3 REGISTER BIT LABEL ADDRESS R63 (3Fh) 14:5 FLL_N[9:0] FLL Control 4 3:0 FLL_GAIN[3:0] Register 3Fh FLL Control 4 REGISTER BIT LABEL ADDRESS R64 ...
Page 196
WM8993 REGISTER BIT LABEL ADDRESS R65 (41h) CLK_DCS_DIV 13:10 Clocking 3 [3:0] SAMPLE_RAT 9:7 E[2:0] 4:1 CLK_SYS_RA TE[3:0] 0 CLK_DSP_EN A Register 41h Clocking 3 w DEFAULT DESCRIPTION DC Servo Clock Divider 1000 0000 = CLK_SYS 0001 = CLK_SYS / ...
Page 197
Pre-Production REGISTER BIT LABEL ADDRESS R66 (42h) 9 DAC_DIV4 Clocking 4 TOCLK_RATE 8 _DIV16 7 TOCLK_RATE _X4 6:1 CLK_256K_DI V[5:0] 0 SR_MODE Register 42h Clocking 4 REGISTER BIT LABEL ADDRESS R69 (45h) 1 CLK_SYS_EN Bus Control A 1 Register 45h ...
Page 198
WM8993 REGISTER BIT LABEL ADDRESS R71 (47h) 14:12 WSEQ_DATA_ Write WIDTH[2:0] Sequencer 1 11:8 WSEQ_DATA_ START[3:0] 7:0 WSEQ_ADDR[ 7:0] Register 47h Write Sequencer 1 REGISTER BIT LABEL ADDRESS R72 (48h) WSEQ_EOS 14 Write Sequencer 2 WSEQ_DELAY 11:8 [3:0] 7:0 WSEQ_DATA[ ...
Page 199
Pre-Production REGISTER BIT LABEL ADDRESS R74 (4Ah) 0 WSEQ_BUSY Write Sequencer 4 Register 4Ah Write Sequencer 4 REGISTER BIT LABEL ADDRESS R75 (4Bh) 5:0 WSEQ_CURR Write ENT_INDEX[5: Sequencer 5 0] Register 4Bh Write Sequencer 5 REGISTER BIT LABEL ADDRESS R76 ...
Page 200
WM8993 REGISTER BIT LABEL ADDRESS R84 (54h) DCS_TRIG_SI 13 DC Servo 0 NGLE_1 12 DCS_TRIG_SI NGLE_0 9 DCS_TRIG_SE RIES_1 DCS_TRIG_SE 8 RIES_0 5 DCS_TRIG_ST ARTUP_1 4 DCS_TRIG_ST ARTUP_0 DCS_TRIG_DA 3 C_WR_1 2 DCS_TRIG_DA C_WR_0 1 DCS_ENA_CH AN_1 0 DCS_ENA_CH AN_0 ...