CS8415A-IZZR Cirrus Logic Inc, CS8415A-IZZR Datasheet - Page 16

• Manufacturer Part Number: CS8415A-IZZR
• Description: Audio DSPs 96 kHz Digital Audio Intrfc Receiver
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-IZZR

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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5.5
5.6
5.7
pulse on RERR, invoke the occurrence of a RERR interrupt, and affect the current audio sample according
to the status of the HOLD bits. The HOLD bits allow a choice of holding the previous sample, replacing the
current sample with zero (mute), or not changing the current audio sample. If a mask bit is set to 0, the error
is masked, which implies the following: its occurrence will not be reported in the receiver error register, will
not induce a pulse on RERR or generate a RERR interrupt, and will not affect the current audio sample. The
QCRC and CCRC errors do not affect the current audio sample, even if unmasked.
Channel Status Data Handling
The first 2 bytes of the Channel Status block are decoded into the Receiver Channel Status register. The
setting of the CHS bit in the Channel Status Data Buffer Control register determines whether the channel
status decodes are from the A channel (CHS = 0) or B channel (CHS = 1).
The PRO (professional) bit is extracted directly. For consumer data, the COPY (copyright) bit is extracted,
and the category code and L bits are decoded to determine SCMS status, indicated by the ORIG (original)
bit. If the category code is set to General on the incoming AES3 stream, copyright will always be indicated
even when the stream indicates no copyright. Finally, the AUDIO bit is extracted and used to set an AUDIO
indicator, as described in the Non-audio Auto-detection section below.
If 50/15 µs pre-emphasis is detected, the state of the EMPH pin is adjusted accordingly.
The encoded channel status bits which indicate sample word length are decoded according to AES3-1992
or IEC 60958. Audio data routed to the serial audio output port is unaffected by the word length settings and
all 24 bits are passed on as received.
Appendix A describes the overall handling of Channel Status and User data.
User Data Handling
The incoming user data is buffered in a user accessible buffer. Received user data may also be output to
the U pin under the control of a control register bit. Depending on the clocking options selected, there may
not be a clock available to qualify the U data output. Figure
bits have been encoded as Q-channel subcode, the data is decoded and presented in 10 consecutive reg-
ister locations. An interrupt may be enabled to indicate the decoding of a new Q-channel block, which may
be read through the control port.
Non-Audio Auto-Detection
An AES3 data stream may be used to convey non-audio data, thus it is important to know whether the in-
coming AES3 data stream is digital audio or not. This information is typically conveyed in channel status bit
1 (AUDIO), which is extracted automatically by the CS8415A. However, certain non-audio sources, such as
AC-3
CS8415A AES3 receiver can detect such non-audio data. This is accomplished by looking for a 96-bit sync
code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F. When the sync code is detect-
ed, an internal AUTODETECT signal will be asserted. If no additional sync codes are detected within the
next 4096 frames, AUTODETECT will be de-asserted until another sync code is detected. The AUDIO bit
in the Receiver Channel Status register is the logical OR of AUTODETECT and the received channel status
bit 1. If non-audio data is detected, the data is still processed exactly as if it were normal audio. It is up to
the user to mute the outputs as required.
®
or MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The
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illustrates the timing. If the incoming user data
CS8415A
DS470F4