CS493253-CLZ Cirrus Logic Inc, CS493253-CLZ Datasheet - Page 21

• Manufacturer Part Number: CS493253-CLZ
• Description: Audio DSPs IC Multi-Standard Audio Decoder
• Manufacturer: Cirrus Logic Inc

Specifications of CS493253-CLZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.14. Switching Characteristics — Parallel Data Input
(VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
Notes: 1. CMPREQ signal is asynchronous to CLKIN and can change at any time relative to CLKIN.
DS339F7
CMPCLK Period
DATA[7:0] setup before CMPCLK high
DATA[7:0] hold after CMPCLK high
Delay from falling edge of CMPREQ to CMPCLK rising edge
DATA[7:0]
CMPREQ
CMPCLK
2. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can
be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/4 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLK == 100ns
DCLK == 65 MHz after boot, i.e. DCLK == 15.4ns
It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.
Figure 11. Parallel Data Timing (when not in a parallel control mode)
Parameter
T
cmpsu
T
cmpclk
Symbol
T
T
T
T
T
reqclk
cmpclk
cmpsu
cmphld
reqclk
L
= 20 pF)
4*DCLK + 10
CS49300 Family DSP
T
cmphld
Min
10
10
0
Max
-
-
-
-
Unit
ns
ns
ns
ns
21