MCP7940N-I/ST Microchip Technology, MCP7940N-I/ST Datasheet - Page 7

• Manufacturer Part Number: MCP7940N-I/ST
• Description: Real Time Clock I2C GP RTCC 64B SRAM
• Manufacturer: Microchip Technology
• Series: -r
• Type: Clock/Calendarr

Specifications of MCP7940N-I/ST

• Features: Alarm, Leap Year, SRAM
• Memory Size: 64B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C
• Voltage - Supply: 1.8 V ~ 5.5 V
• Voltage - Supply, Battery: 1.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.0
3.1
The MCP7940N supports a bidirectional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
Start and Stop conditions, while the MCP7940N works
as slave. Both master and slave can operate as
transmitter or receiver but the master device
determines which mode is activated.
3.1.1
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined
3.1.1.1
Both data and clock lines remain high.
3.1.1.2
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
FIGURE 3-1:
 2011 Microchip Technology Inc.
is not busy.
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
SCL
SDA
(Figure
(A)
I
I
BUS CHARACTERISTICS
2
2
C Interface
C BUS CHARACTERISTICS
Bus not Busy (A)
Start Data Transfer (B)
Condition
Start
(B)
3-1).
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Acknowledge
Address or
Valid
(D)
to Change
Allowed
Data
3.1.1.3
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
3.1.1.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
3.1.1.5
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable-low during the high period of
the Acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (MCP7940N) will leave the data line high to
enable the master to generate the Stop condition.
Stop Data Transfer (C)
Data Valid (D)
Acknowledge
(D)
MCP7940N
DS25010A-page 7
Condition
Stop
(C)
(A)